R&D: Enhancement of ISPP Efficiency Using Neural Network-Based Optimization of 3D NAND Cell

IEEE Transactions on Electron Devices has published an article written by Kyeongrae Cho, Hyeok Yun, Kihoon Nam, Chanyang Park, Hyundong Jang, Jun-Sik Yoon, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea, Hyun-Chul Choi, Department of Electronic Engineering, Yeungnam University, Gyeongsan, South Korea, Min Sang Park, SK hynix Inc, Icheon, South Korea, and Rock-Hyun Baek, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea.

Abstract: “The enhancement of program efficiency is essential for fast NAND cell operation. However, it is difficult to simultaneously consider many factors, such as structural parameters and trap characteristics, having complex relationships. To overcome these problems, we proposed a neural network (NN)-applied optimization method. First, an optimal network structure was selected by comparing the network performance and learning time. The selected network accurately predicted the threshold voltages of the 21 states of a single NAND cell within a second. Next, an optimization method to improve program efficiency is suggested. The improved NAND cell structure is obtained using a trained NN and numerical method. Here, the optimization required only a few minutes for one optimization process and could consider all parameters simultaneously. Finally, the optimized NAND cell was evaluated using a technology computer-aided design (TCAD) simulation, and its program efficiency was verified. This study shows a specific example of machine learning applied to the semiconductor area, especially in NAND flash memory.“