R&D: Improvement of GIDL-Assisted Erase by Using Surrounded BL PAD Structure for VNAND

2023 IEEE International Memory Workshop (IMW) has published an article written by Suhwan Lim, Samki Kim, Changhee Lee, Hyeongwon Choi, Nambin Kim, Jaehun Jung, Hanvit Yang, Tae-Hun Kim, Junhee Lim, Daewon Ha, Sunghoi Hur, Jaehoon Jang, Yu-Gyun Shin, and Jaihyuk Song, Samsung Electronics Co., Ltd, Hwaseong-si, Gyeonggi-do, Republic of Korea.

Abstract: “We propose a novel structure to enhance transverse band-to-band tunneling (T-BTBT) for the erase scheme assisted by gate induced drain leakage (GIDL) to improve the erase speed of high density vertical NAND (VNAND). In order to increase the GIDL current, we adopt the structure, in which the bit-line PAD (BL PAD) is surrounded by the GIDL transistors, to the top part of the VNAND memory string. In this structure, the n+−doped region called the BL PAD is pulled down so that its bottom is placed below the bottom of the first GIDL transistor and the gate-to-drain overlap area is increased. Furthermore, the n+−doped poly-Si region of the BL PAD is covered with the undoped poly-Si layer to reduce the n type doping concentration in the overlap region between the BL PAD and GIDL transistor. Thus, the depletion region is formed between the n+−doped BL PAD and undoped channel poly-Si regions. Then, in contrast to the conventional structure where the longitudinal BTBT (L-BTBT) current dominates, the TBTBT current occurs in such a depletion region and becomes the dominant GIDL current. The proposed structure on a VNAND device array is experimentally verified, and we obtain the GIDL current which is 5 times larger than that in VNAND to which the conventional ion implantation structure applied. Such a large GIDL current is suitable even for VNAND with more than 1000 layers of word line stacked.“