R&D: Distributed Cycling in Charge Trap-Based 3D NAND Arrays, Model and Qualification Tests Implications

2023 IEEE International Memory Workshop (IMW) has published an article written by Gianluca Nicosia, Niccolò Righetti, and Yingda Dong, NAND Technology Development, Micron Technology, Inc. Boise, ID, USA.

Abstract: “In this work, we present the first electrical characterization and modeling of the impact on long-term data retention of distributed cycling in charge trap (CT) 3D NAND arrays. Dependence on Program/Erase cycling conditions of trapassisted tunneling (TAT), charge detrapping, and lateral charge migration (LCM) are experimentally evaluated and modeled. It is demonstrated that post-cycling TAT degradation depends only on the overall cycling dose and not on cycling temperature nor on the delays in-between each Program/Erase operation. On the other hand, charge detrapping follows the same time and temperature dynamics as the ones observed in floating-gate NAND arrays. Finally, LCM is observed to improve with increasing cycling dose and cycling temperature but to be negligibly dependent on the cycling duration. Results are a cornerstone in designing accelerated cycling tests for CT 3D NAND arrays qualification.“