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The Regents of University of California Assigned Two Patents

Topological spin textures in 3D magnetic structures, voltage-controlled gain-cell magnetic memory

Topological spin textures in 3D magnetic structures
The Regents of the University of California, Oakland, CA, has been assigned a patent (11742307) developed by Liu, Kai, Falls Church, VA, for a topological spin textures in 3-dimensional magnetic structures.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Utilizing the topological character of patterns in 3D structures is beneficial for information storage, magnetic memory and logic systems. One embodiment describes the use of topological knots, exemplified by a Möbius strip, in which a spin traversing along the band for a complete cycle will recover its original position, while having rotated away from its original orientation. The spins can respond to an external magnetic field, but cannot achieve a ferromagnetic state, in which all magnetic moments are pointing in the same direction, due to the topological knot. 3D assemblies of such nano-Möbius strips may form prototype secure magnetic information storage devices that are secure and with extremely low levels of energy dissipation.

The patent application was filed on 2021-09-09 (17/470856).

Voltage-controlled gain-cell magnetic memory
The Regents of the University of California, Oakland, CA, has been assigned a patent (11742011) developed by Salahuddin, Sayeef, Walnut Creek, CA, and Sayed, Shehrin, Berkeley, CA, for a voltage-controlled gain-cell magnetic memory.

The abstract of the patent published by the U.S. Patent and Trademark Office states: The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 MΩ, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

The patent application was filed on 2021-08-11 (17/399583).

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