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R&D: Lightweight Read Reference Voltage (RRV) Calibration Strategy for Improving 3D TLC NAND Flash Memory Reliability

Experiment results show that predicted RRV using proposed strategy is close to actual optimal RRV, reducing raw bit error rate of same model of flash memory by up to 93%.

IEEE Transactions on Device and Materials Reliability has published an article written by Hua Feng, Debao Wei, Yongchao Wang, Yu Song, Zhelong Piao, and Liyan Qiao, School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin, China.

Abstract: Flash memory has gradually become the dominant storage device in the consumer market and data centers since the storage capacity increases and production costs decline. Unfortunately, as the bit density of flash memory increased, the severity of reliability issues has escalated. Read retry is necessary to recover high bit-error-rate flash data; however, read retry requires the flash to perform sequential read operations, which significantly increases read latency. To improve the flash memory read performance, a reliable adaptive optimization strategy for flash memory read reference voltage (RRV) is urgently needed. In this paper, we performed a full range of error characterization tests on three-dimensional (3-D) triple-level cell (TLC) flash memory, focusing on the effects of retention leakage, P/E wear, and interlayer variation on the threshold voltage. Finally, a lightweight flash memory RRV calibration strategy was constructed. The experiment results show that the predicted RRV using the proposed strategy is very close to the actual optimal RRV, reducing the raw bit error rate (RBER) of the same model of flash memory by up to 93.2%.