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R&D: Monitor Units Assisted LDPC Decoding Algorithm Based on Page BER Variation of 3D NAND Flash Memory

Compared with conventional LDPC scheme, proposed algorithms extend lifetime by up to 5.83x and reduce decoding iterations by up to 78.63%.

Microelectronics Reliability has published an article written by Bo Zhang, Qi Wang, Xianliang Wang, Xiaolei Yu, Qianhui Li, Jing He, Zongliang Huo, and Tianchun Ye, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China, and University of Chinese Academy of Sciences, Beijing 100049, China.

Abstract: With the increase of retention time and program/erase (P/E) cycles, the reliability of 3D NAND Flash memory with large storage capacity degrades. Because of its excellent error correction capability, the low density parity check (LDPC) code has become the mainstream method for solving reliability problems in modern NAND Flash memory. However, the log-likelihood ratio (LLR) obtained by the conventional scheme is not accurate enough to guarantee decoding performance. Moreover, page bit error rate (BER) variation exacerbates LLR inaccuracy. To solve these problems, we propose a Monitor-Units BER Calibrated LDPC (MBCL) algorithm, which adds additional data as monitor units (MUs) to monitor the change of BER in pages and get more accurate LLR values. On this basis, we propose an All State BER Estimation LDPC (ABEL) algorithm to utilize the BER obtained by MUs to estimate the BER of all other voltage states. It reduces the storage overhead of the MBCL algorithm. Compared with the conventional LDPC scheme, the proposed algorithms extend the lifetime by up to 5.83 times and reduce the decoding iterations by up to 78.63%.“

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