R&D: Hierarchical Cache Configuration Based on Hybrid SOT- and STT-MRAM

AIP Advances has published an article written by Shaopu Han, Qiguang Wang, and Yanfeng Jiang, Department of Electrical Engineering, School of Internet of Things (IoT) Engineering, Jiangnan University, Wuxi, Jiangsu 214122, China, and Institute of Advanced Technology, Jiangnan University, Wuxi, Jiangsu 214122, China.

Abstract: “With the rapid growth of big data information and the continuous iteration progress of CPU architecture, the implementation of a new memory-based cache architecture is urgent and challenging. In the paper, a CPU cache architecture system based on MRAM is built. Firstly, the performance of SRAM, STT-MRAM and SOT-MRAM as caches from 8 kb to 32 Mb is evaluated. Secondly, by summarizing the performance of SRAM and MRAM in different cache levels, a new quad-core CPU cache architecture design scheme with SOT-MRAM as the first level of cache and STT-MRAM as the second level of cache is determined. Thirdly, the built cache system is simulated. A non-inclusive strategy is proposed to replace the inclusive strategy in order to solve the problem of high dynamic energy of STT-MRAM at the second level. The idea of having a quad-core CPU dynamically share the second-level cache is proposed in the paper. Finally, the caching system in the paper is compared with the other previous works, showing up to 60.78% energy consumption advantage and 33.22% leakage power advantage. The proposed MRAM-based CPU cache system and the corresponding cache strategy have potential application with the benefits of low power and less area.“