IEEE Transactions on Electron Devices has published an article written by Yohan Kim, Department of Semiconductor and Display Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea, and Computational Science and Engineering Team, Innovation Center, Samsung Electronics, Suwon, South Korea, and SoYoung Kim, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea.
Abstract: “This article presents the accurate compact modeling methodology to optimize the gate-induced drain leakage (GIDL)-assisted erase operation for vertical stack-up, multiple stack, and Z -directional shrink of the 3-D vertically integrated NAND (V-NAND) flash memory. The artificial neural network (ANN) is initially applied in the V-NAND transistors to describe the various GIDL characteristics with channel profile variations. In addition, physics-based RC network models are investigated to accurately model the complex process in the state-of-the-art V-NAND products. All models are implemented in Verilog-A, and the time dynamics of the GIDL-assisted channel potential increase for erase operations are successfully reproduced in the SPICE simulations. This SPICE-compatible compact model is essential to the design technology co-optimization (DTCO) for over 200-layer V-NAND, because the RC delay-related erase failures have become an important issue in the high aspect ratio (HAR) channel holes. Based on the proposed compact model, the highly accurate GIDL-assisted erase simulations are performed, and an erase optimization procedure is demonstrated with GIDL injection level, physical etch limit, and Z shrink rate in the next V-NAND candidate structures. Therefore, this process-aware compact model is a valuable tool for pathfinding activities in the early stage of 3-D V-NAND flash memory development.“