Mellanox/Nvidia Assigned Two Patents

DMA engine for diagnostic data
Mellanox Technologies, Ltd., Yokneam, Israel, (acquired by Nvidia Corp.) has been assigned a patent (11637739) developed by Aibester, Niv, Herzliya, Israel, Kfir, Aviv, Nili, Israel, Levy, Gil, Hod Hasharon, Israel, and Mula, Liron, Ramat Gan, Israel, for a “Direct Memory Access (DMA) engine for diagnostic data.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A network-connected device includes at least one communication port, packet processing circuitry and Diagnostics Direct Memory Access (DMA) Circuitry (DDC). The at least one communication port is configured to communicate packets over a network. The packet processing circuitry is configured to receive, buffer, process and transmit the packets. The DDC is configured to receive a definition of (i) one or more diagnostic events, and (ii) for each diagnostic event, a corresponding list of diagnostic data that is generated in the packet processing circuitry and that pertains to the diagnostic event, and, responsively to occurrence of a diagnostic event, to gather the corresponding list of diagnostic data from the packet processing circuitry.”

The patent application was filed on 2021-01-10 (17/145341).

Multi-socket network interface controller with consistent transaction ordering
Mellanox Technologies, Ltd., Yokneam, Israel, (aquired by Nvidia Corp.), has been assigned a patent (11620245) developed by Oved, Tzahi, Ramat Gan, Israel, Shochat, Achiad, Rosh Pina, Israel, Liss, Liran, Atzmon, Israel, Bloch, Noam, Bat Shlomo, Israel, Heller, Aviv, Rishon LeZion, Israel, Burstein, Idan, Akko, Israel, Shahar, Ariel, Jerusalem, Israel, and Paneah, Peter, Nesher, Israel, for a “multi-socket network interface controller with consistent transaction ordering.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.”

The patent application was filed on 2021-10-18 (17/503392).