SEE-MAPLD Workshop: Avalanche Technology Presents Solutions for Satellite Mission Adaptability

Avalanche Technology, Inc. continues to demonstrate support for the Radiation Hardened Electronics Community by sharing valued solutions to longstanding challenges and evolving threats.

Paul Chopelas, GM, Avalanche, presents solutions enabling satellite mission adaptability at the upcoming Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop. Held in La Jolla, CA, May 17 and 18, SEE MAPLD is a joint workshop focusing on single event radiation effects in microelectronics combined with increasing need for and use of programmable logic devices in aerospace and defense applications.

SEE MAPLD brings together academic, government and commercial interests to examine the latest research and the newest microelectronics technologies available to bolster resilience, capability and adaptability of aerospace and defense systems, primarily for space environments. Supremacy in space depends on compact, reliable, scalable, versatile hardware platforms that can adapt to evolving mission requirements and respond to threats in real time, both natural and man made. Until recently, prior limitations of processing and memory technology have historically rendered this aspiration impossible. Innovations on a variety of fronts, including advanced Adaptive SoCs from AMD/Xilinx and others, advancements in artificial intelligence and radiation resilient memory technology are chief among them.

Specifically, combining all 3, the company’s MRAM-based boot module solutions now allow the use of Firmware Over-The-Air (FOTA) updates and multiple code images for advanced AMD/Xilinx adaptive SoC platforms used in space-based applications such as Versal and UltraScale. Leveraging disruptive Gen 3 Space Grade Dual QSPI Persistent SRAM (P-SRAM) family with its robust, yet flexible write protection schemes, industry endurance (10^16) and pin compatible density options shipping today from 1Gb to 8Gb, these satellite architectures can now mirror the simplicity of terrestrial systems. The combined solution allows re-imagined satellite system architectures now capable of mission adaptability, enhanced resilience and real time responsiveness.

“Avalanche Technology continues to listen and respond to the needs of the Aerospace & Defense community in order to provide these valued solutions on a commercial timeline,” said Chopelas. “We’re delighted to be recognized consistently by our customers as “the silver bullet” for applications like this. When we combine game changing technology with innovative productization methodology and a genuine desire to contribute to the ecosystem, magic can happen. I look forward to exchanging learnings and new ideas with the community at SEE MAPLD.”

Avalanche Gen 3 Space Grade MRAMs
The Gen 3 Space Grade families are offered as a standard product in parallel with asynchronous SRAM-compatible timing and dual QSPI high speed serial interface in various density options from 1Gb to 8Gb. Designed for reliability with multi-bit error correction and 10^16 write cycle endurance, data is always non-volatile. The devices are offered in small footprint packaging and extended operating temperature range (-40°C to 125°C) with a JEDEC qualification flow, where every device goes through a 48-hour burn in before being shipped to customers. There are additional qualification screening and packaging options available through partners.