Kepler Computing Assigned Five Patents

NAND based sequential circuit with ferroelectric or paraelectric material
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11611345) developed by Mathuriya, Amrita, Portland, OR, Odinaka, Ikenna, Durham, NC, Dokania, Rajeev Kumar, Beaverton, OR, Rios, Rafael, Austin, TX, and Manipatruni, Sasikanth, Portland, OR, for a “NAND based sequential circuit with ferroelectric or paraelectric material.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.”

The patent application was filed on 2021-08-20 (17/407972).

Pulsing scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line to minimize read or write disturb effects
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11610620) developed by Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for a “pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line to minimize read or write disturb effects.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.”

The patent application was filed on 2021-11-18 (17/530362).

Pulsing scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11610619) developed by Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for a “pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.”

The patent application was filed on 2021-11-18 (17/530363).

Compare logic based sequential circuit with ferroelectric or paraelectric material
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11545979) developed by Mathuriya, Amrita, Portland, OR, Odinaka, Ikenna, Durham, NC, Dokania, Rajeev Kumar, Beaverton, OR, Rios, Rafael, Austin, TX, and Manipatruni, Sasikanth, Portland, OR, for a “compare logic based sequential circuit with ferroelectric or paraelectric material.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.”

The patent application was filed on 2021-08-20 (17/408000).

Majority logic gate with input paraelectric capacitors
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11539368) developed by Manipatruni, Sasikanth, Portland, OR, Rios, Rafael, Austin, TX, Odinaka, Ikenna, Durham, NC, Menezes, Robert, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Ramesh, Ramamoorthy, Moraga, CA, and Mathuriya, Amrita, Portland, OR, for a “compare logic based sequential circuit with ferroelectric or paraelectric materia.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.”

The patent application was filed on 2021-05-11 (17/317482).