STmicroelectronics Assigned Patent
Writing in NVM according to ageing of memory cells and corresponding integrated circuit
By Francis Pelletier | May 4, 2023 at 2:00 pmSTmicroelectronics S.r.l., Agrate Brianza, Italy, and STmicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11615857) developed by La Rosa, Francesco, Rousset, France, Castaldo, Enrico, Catania, Italy, Grande, Francesca, Syracuse, Italy, Pagano, Santi Nunzio Antonino, Catania, Italy, Nastasi, Giuseppe, and Italiano, Franco, San Filippo del Mela, Italy, for a “method for writing in a non-volatile memory according to the ageing of the memory cells and corresponding integrated circuit.”
The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.”
The patent application was filed on 2021-04-06 (17/224024).
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