R&D: Intrablock Wear Leveling to Counter Layer-to-Layer Endurance Variation of 3D NAND Flash Memory

IEEE Transactions on Electron Device has published an article written by Md Raquibuzzaman, Aleksandar Milenkovic, and Biswajit Ray, Department of Electrical and Computer Engineering, The University of Alabama in Huntsville, Huntsville, AL, USA.

Abstract: “A shift to 3-D NAND technology has resulted in flash memory blocks that include many pages, leading to “big-block” management issues in storage systems. This article experimentally explores endurance variability in 3-D NAND flash memory blocks and finds that pages in the bottom and top layers exhibit lower endurance than pages in the middle layers. We find that erase threshold voltage ( Vt) variation between the layers is the root cause for the observed endurance variation. This variation in endurance among pages can cause severe underutilization of flash memory. To counter these effects and improve the overall utilization of 3-D NAND flash memories, we propose an intrablock wear-leveling algorithm based on dynamic, incremental, and layer-aware downsizing of flash memory blocks.“