Silicon Storage Technology Assigned Ten Patents

Forming device with split gate NVM cells, HV devices having planar channel regions and FINFET logic devices
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (11594453) developed by Jourba, Serguei, Aix en Provence, France, Decobert, Catherine, Pourrieres, France, Zhou, Feng, Fremont, CA, Kim, Jinho, Saratoga, CA, Liu, Xian, Sunnyvale, CA, and Do, Nhan, Saratoga, CA, for a “method of forming a device with split gate non-volatile memory cells, HV devices having planar channel regions and FINFET logic devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.”

The patent application was filed on 2022-04-08 (17/716950).

Precision programming circuit for analog neural memory in DL artificial neural network
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (11586898) developed by Tran, Hieu Van, Vu, Thuan, Trinh, Stephen, Hong, Stanley, and Ly, Anh, San Jose, CA, for a “precision programming circuit for analog neural memory in deep learning artificial neural network.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.”

The patent application was filed on 2019-03-21 (16/360733).

Redundant memory access for rows or columns containing faulty memory cells in analog neural memory in DL artificial neural network
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (11568229) developed by Tran, Hieu Van, Hong, Stanley, Vu, Thuan, Ly, Anh, San Jose, CA, Pham, Hien, Nguyen, Kha, and Tran, Han, Ho Chi Minh, Vietnam, for a “precision programming circuit for analog neural memory in deep learning artificial neural network.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.”

The patent application was filed on 2018-10-03 (16/151259).

Architectures for storing and retrieving system data in NVM system
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (11538532) developed by Liu, Xian, Sunnyvale, CA, Wang, Chunming, Shanghai, China, Do, Nhan, Saratoga, CA, and Tran, Hieu Van, San Jose, CA, for “architectures for storing and retrieving system data in a non-volatile memory system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.”

The patent application was filed on 2021-03-11 (17/199383).

Precision tuning of page or word of NVM cells and associated high voltage circuits for analog neural memory array in artificial neural network
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (11532354) developed by Tran, Hieu Van, Vu, Thuan, Trinh, Stephen, Hong, Stanley, Ly, Anh, San Jose, CA, Lemke, Steven, Boulder Creek, CA, Tiwari, Vipin, Dublin, CA, and Do, Nhan, Saratoga, CA, for “precision tuning of a page or word of non-volatile memory cells and associated high voltage circuits for an analog neural memory array in an artificial neural network.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.”

The patent application was filed on 2020-09-17 (17/024410).

Temperature compensation in analog memory array by changing threshold voltage of selected memory cell in array
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (11521682) developed by Tran, Hieu Van, San Jose, CA, Lemke, Steven, Boulder Creek, CA, Do, Nhan, Saratoga, Tiwari, Vipin, Dublin, CA, and Reiten, Mark, Alamo, CA, for a “temperature compensation in an analog memory array by changing a threshold voltage of a selected memory cell in the array.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.”

The patent application was filed on 2020-11-11 (17/095661).

Configurable input blocks and output blocks and physical layout for analog neural memory in DL artificial neural network
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (11507642) developed by Tran, Hieu Van, Trinh, Stephen, Vu, Thuan, Hong, Stanley, San Jose, CA, Tiwari, Vipin, Dublin, CA, Reiten, Mark, Alamo, CA, and Do, Nhan, Saratoga, CA, for “configurable input blocks and output blocks and physical layout for analog neural memory in deep learning artificial neural network.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.”

The patent application was filed on 2019-06-21 (16/449201).

Precision tuning for programming of analog neural memory in DL artificial neural network
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (11507816) developed by Tran, Hieu Van, San Jose, CA, Lemke, Steven, Boulder Creek, CA, Tiwari, Vipin, Dublin, CA, Do, Nhan, Saratoga, CA, and Reiten, Mark, Alamo, CA, for a “precision tuning for the programming of analog neural memory in a deep learning artificial neural network.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.”

The patent application was filed on 2019-09-19 (16/576533).