Samsung Electronics Assigned Seventeen Patents

OTP memory and storage device
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11545228) developed by Kim, Hyung Seuk, Seongnam-si, Korea, for “OTP memory and storage device including the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device may include a one time programmable (OTP) memory including a plurality of OTP cells and configured to store OTP key values in the plurality of OTP cells, and an erase instruction circuit that is detachably mounted on the storage device and connected to a first node of the OTP memory. When the erase instruction circuit is removed from the storage device, the OTP memory may be configured to receive the erase instruction signal having a first logic level at the first node and permanently erase all the OTP key values stored in the plurality of OTP cells by programming the plurality of OTP cells to an identical OTP key value in response to the erase instruction signal having the first logic level.”

The patent application was filed on 2021-01-11 (17/145636).

Storage device for mapping virtual streams onto physical streams
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11544181) developed by Yong, Hwanjin, and Kim, Jin-Soo, Seoul, Korea, for “storage device for mapping virtual streams onto physical streams and method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device includes a controller and nonvolatile memories. The controller receives write commands having virtual stream identifiers (IDs), receives discard commands having the virtual stream IDs, and determines a lifetime of write data to which each of the virtual stream IDs is assigned. The nonvolatile memories are accessed by the controller depending on physical stream IDs. The controller maps the virtual stream IDs and the physical stream IDs based on the lifetime of the write data.”

The patent application was filed on 2019-01-09 (16/243795).

NVM and operating method
Samsung Electronics Co., Ltd., Gyeong Gi-do, Korea, has been assigned a patent (11545224) developed by Kim, Yumin, Kim, Seyun, Kim, Jinhong, Seoul, Korea, Mizusaki, Soichiro, and Cho, Youngjin, Suwon-si, Korea, for “nonvolatile memory device and operating method of the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.”

The patent application was filed on 2021-05-03 (17/306302).

Mobile storage
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11546000) developed by Berman, Amit, Ramat Gan, Israel, Doubchak, Ariel, Herzliya, Israel, Haim, Eli, Raanana, Israel, and Blaichman, Evgeny, Tel Aviv, Israel, for a “mobile data storage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.”

The patent application was filed on 2020-05-04 (16/865891).

Non-volatile dual inline memory module (NVDIMM) for supporting DRAM cache mode
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11537521) developed by Lim, Sunyoung, Hwaseong-si, Korea, for “non-volatile dual inline memory module (NVDIMM) for supporting dram cache mode and operation method of NVDIMM.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.”

The patent application was filed on 2020-05-18 (16/876890).

NVM which utilizes pulse applied to bit line and/or common source line between read operations to reduce noise
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11538533) developed by Han, Gu Yeon, Suwon-si, Korea, Kang, Jin-Kyu, Seoul, Korea, Lee, Rae Young, Suwon-si, Korea, Park, Se Jun, Yongin-si, Korea, and Lee, Jae Duk, Seongnam-si, Korea, for a “non-volatile memory device which utilizes a pulse applied to a bit line and/or a common source line between read operations to reduce noise.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line, a common source line driver configured to supply a common source line voltage to the common source line, a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines, a control logic circuit configured to adjust the common source line voltage and the bit line voltage, and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.”

The patent application was filed on 2021-04-19 (17/233858).

Static random access memory of 3D stacked devices
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11538814) developed by Hwang, Inchan, Schenectady, NY, and Jun, Hwichan, Clifton Park, NY, for a “static random access memory of 3D stacked devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a static random access memory (SRAM) including a plurality of transistors disposed in a first layer and a second layer. The first layer includes a first shared gate of a first transistor and a second shared gate of a second transistor, among the plurality of transistors. The second layer is disposed above the first layer and includes a third shared gate of a third transistor and a fourth shared gate of a fourth transistor, among the plurality of transistors. The third shared gate is disposed above the first shared gate, and the fourth shared gate is disposed above the second shared gate. The SRAM further includes a first shared contact, a second shared contact, a first cross-couple contact connecting the fourth shared gate and the first shared contact, and a second cross-couple contact connecting the third shared gate and the second shared contact.”

The patent application was filed on 2021-04-23 (17/239060).

Storage device inferring read levels based on artificial neural network model and learning method of artificial neural network mode
Samsung Electronics Co., Ltd., Gyeonggi-do, Korea, has been assigned a patent (11537842) developed by Oh, Hyunkyo, Yongin-si, Korea, and Seo, Youngdeok, Seoul, Korea, Song, Jinbaek, Hwaseong-si, Korea, and Choi, Sanghyun, Seoul, Korea, for “storage device inferring read levels based on artificial neural network model and learning method of artificial neural network mode.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device includes a non-volatile memory including a plurality of blocks, a buffer memory that stores a plurality of on-cell counts, which are generated by reading memory cells connected to a plurality of reference word lines of the plurality of blocks by using a read level, and an artificial neural network model, and a controller that inputs an on-cell count corresponding to a target block among the plurality of on-cell counts and a number of a target word line of the target block to the artificial neural network model, and infers a plurality of read levels for reading data of memory cells connected to the target word line using the artificial neural network model.”

The patent application was filed on 2019-06-21 (16/448636).

Operation method of NVM device
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11532365) developed by Yu, Jae-Duk, Seoul, Korea, Nam, Sang-Wan, Park, Jonghoon, Hwaseong-si, Korea, and Lee, Ho-Jun, Uiwang-si, Korea, for an “operation method of nonvolatile memory device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.”

The patent application was filed on 2021-07-15 (17/377141).

3D semiconductor memory
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11532639) developed by Lee, Sangsoo, Seongnam-si, Korea, Kim, Chaeho, Seoul, Korea, Lee, Woosung, Yongin-si, Korea, Nam, Phil Ouk, Suwon-si, Korea, and Jee, Junggeun, Siheung-si, Korea, for a “three-dimensional semiconductor memory device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.”

The patent application was filed on 2020-09-29 (17/036594).

Memory controller, system and operating method of memory system for scheduling data access across channels of memory chips within memory system
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11531630) developed by Park, Ikkyun, Suwon-si, Korea, Shin, Soongmann, and Choe, Gyuseok, Hwaseong-si, Korea, for “memory controller, memory system and operating method of the memory system for scheduling data access across channels of memory chips within the memory system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips, obtaining information about an operation status of each of the plurality of memory chips, and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.”

The patent application was filed on 2020-10-23 (17/078194).

Memory modules and memory systems having same
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11531496) developed by Kwon, Yongsuk, Goyang-si, Korea, So, Jinin, Hwaseong-si, Korea, Lee, Jonggeon, Kim, Kyungsoo, Jung, Jin, Seoul, Korea, and Cho, Jeonghyeon, Hwaseong-si, Korea, for “memory modules and memory systems having the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.”

The patent application was filed on 2021-01-21 (17/154030).

Storage devices and methods of operating
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11532366) developed by Park, Jiwoon, Suwon-si, Korea, and Choi, Jaehyurk, Jeonju-si, Korea, for “storage devices and methods of operating storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device includes a semiconductor memory device and a storage controller. The semiconductor memory device receives write data based on a data strobe signal and data signals, and outputs read data based on the data strobe signal and the data signals. The storage controller transmits the data strobe signal and the data signals in parallel to the semiconductor memory device through signal lines. The storage controller includes a first delay circuit that delays the data signals such that some edges of windows of the data signals on the signal lines are desynchronized by first skew offsets which are different from one another.”

The patent application was filed on 2021-03-15 (17/201761).

NVM, storage device including same, and read method
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11532361) developed by Kim, Minseok, and Kim, Hyunggon, Hwaseong-si, Korea, for “non-volatile memory device, storage device including the same, and read method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device receives a read command and an address from a controller, and performs a data recovery read operation in response to the read command. In the data recovery read operation, an operation of obtaining aggressor group information from a memory cell connected to a word line adjacent to a word line selected according to the address, and an operation of recovering data corresponding to the obtained aggressor group information in a memory cell connected to the word line selected according to the address, are repeatedly performed on each of a plurality of aggressor groups.”

The patent application was filed on 2021-07-20 (17/380289).

Vertical memory device including substrate control circuit and memory system including same
Samsung Electronics Co., Ltd., Gyeonggi-do, Korea, has been assigned a patent (11532634) developed by Shim, Sang-won, and Lim, Bong-soon, Seoul, Korea, for “vertical memory device including substrate control circuit and memory system including the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.”

The patent application was filed on 2018-07-16 (16/035995).

NVM with page buffer circuit supporting read operation of improved reliabilty
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11527295) developed by Bang, Jinbae, Anyang-si, Korea, Kim, Doohyun, Kim, Minseok, and Kim, Jisu, Hwaseong-si, Korea, for “nonvolatile memory device with page buffer circuit supporting read operation of improved reliabilty.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”

The patent application was filed on 2021-03-12 (17/200557).

NVM and method of programming
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11527293) developed by Park, Jungmin, Seoul, Korea, Sung, Kyunghoon, Seongnam-si, Korea, Park, Ilhan, Suwon-si, Korea, Lee, Jisang, Iksan-si, Korea, Jang, Joon Suc, Hwaseong-si, Korea, and Joo, Sanghyun, Suwon-si, Korea, for “nonvolatile memory device and method of programming in the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.”

The patent application was filed on 2021-06-08 (17/341837).