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Mosaid Technologies Assigned Patent

Erasing memory cells in flash memory device using positive well bias voltage and negative word line voltage

Mosaid Technologies Inc., Ottawa, ONT, Canada, has been assigned a patent (11594281) developed by Chen, Chung-Zen, Hsinchu, Taiwan, Lin, Yang-Chieh, Tainan, Taiwan, and Kuo, Chung-Shan, Shulin, Taiwan, for a method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

The patent application was filed on 2021-01-21 (17/154241).

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