TSMC Assigned Nineteen Patents

3D memory and manufacturing
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11538862) developed by Wu, Chao-I, Zhubei, Taiwan, and Lin, Yu-Ming, Hsinchu, Taiwan, for “three-dimensional memory device and manufacturing method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.”

The patent application was filed on 2020-12-01 (17/108243).

Semiconductor memory structure and manufacturing
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11538832) developed by Lin, Meng-Han, Hsinchu, Taiwan, for “semiconductor memory structure and method of manufacturing the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory structure and method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure comprises a cell array region, at least one connection region formed beside the cell array region and an interconnect structure formed on the connection region. The connection region comprises staircase portions and interval portions, which are alternately arranged and are separated by ferroelectric layers. The staircase portion comprises a staircase structure of alternating insulating layers and conductive layers, a dielectric layer formed on the staircase structure, and first conductive pillars formed over the staircase structure, extending into the dielectric layer and in contact with the staircase structure. The interval portion is formed beside the staircase portion and comprises second conductive pillars. The interconnect structure comprises vias formed on the first conductive pillars and the second conductive pillars in a XY staggered pattern.”

The patent application was filed on 2021-01-05 (17/142152).

Memory, method of forming, and memory array
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11538858) developed by Lee, Chien-Min, Hsinchu County, Taiwan, Song, Ming-Yuan, Huang, Yen-Lin, Hsinchu, Taiwan, Lin, Shy-Jay, Hsinchu County, Taiwan, Lee, Tung-Ying, Hsinchu, Taiwan, and Bao, Xinyu, Fremont, CA, for “memory device, method of forming the same, and memory array.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Provided are a memory device and a method of forming the same. The memory device includes: a selector, a magnetic tunnel junction (MTJ) structure, disposed on the selector, a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector, a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure, a word line, electrically coupled to a gate of the transistor, a bit line, electrically coupled to the SOT layer, a first source line, electrically coupled to a source of the transistor, and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.”

The patent application was filed on 2021-06-29 (17/362979).

3D cross-bar NVM
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11532705) developed by Colinge, Jean-Pierre, Hsinchu, Taiwan, Diaz, Carlos H., Mountain View, CA, and Guo, Ta-Pen, Taipei, Taiwan, for a “3D cross-bar nonvolatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.”

The patent application was filed on 2020-07-06 (16/921606).

Forming semiconductor memory structure
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11532339) developed by Chien, Jui-Fen, Taichung, Taiwan, Yeh, Hanwen, Hsinchu, and Lin, Tsann, Hsinchu, Taiwan, for a “method for forming semiconductor memory structure.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for forming a semiconductor memory structure is provided. The method includes following operations. An interlayer is formed over a first ferromagnetic layer, wherein forming the interlayer includes following operations. A first metal film is formed by sputtering a first target material. A first oxygen treatment is conducted to the first metal film to form a first metal oxide film. A second metal oxide film is formed over the first metal oxide film by sputtering a second target material different from the first target material. A second metal film is formed by sputtering a third target material. A second oxygen treatment is conducted to the second metal film to form a third metal oxide film.”

The patent application was filed on 2020-06-15 (16/902218).

Memory device and power management
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11532335) developed by Jain, Sanjeev Kumar, Ottawa, Canada, for “memory device and power management method using the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic during the power saving mode of the memory device.”

The patent application was filed on 2020-09-25 (17/031925).

Memory array including dummy regions
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11532343) developed by Young, Bo-Feng, Taipei, Taiwan, Yeong, Sai-Hooi, Wu, Chao-I, Zhubei, Taiwan, Wang, Sheng-Chen, and Lin, Yu-Ming, Hsinchu, Taiwan, for a “memory array including dummy regions.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line, an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line, a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line, and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.”

The patent application was filed on 2020-10-06 (17/064279).

Memory cell with temperature modulated read voltage
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11532357) developed by Wu, Chao-I, Zhubei, Taiwan, and Khwa, Win-San, Hsin-Chu, Taiwan, for a “memory cell with temperature modulated read voltage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An integrated chip has an array of memory cells disposed over a semiconductor substrate and a driver circuit. The driver circuit provides the array with a read voltage that varies in relation to an approximate temperature of the memory array to ameliorate temperature dependencies in read currents. The driver circuit may vary the read voltage in an inverse relationship with temperature. The read voltage may be varied continuous or stepwise and the driver circuit may use a table lookup. Optionally, the driver circuit measures a current and modulates the read voltage until the current is within a target range. The memory cells may be multi-level phase change memory cells that include a plurality phase change element disposed between a bottom electrode and a top electrode. Modulating the read voltage to reduce temperature-dependent current variations is particularly useful for multi-level cells.”

The patent application was filed on 2021-01-15 (17/149985).

NVM with reduced area
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11532752) developed by Chang, Meng-Sheng, Huang, Chia-En, Yang, Yao-Jen, Hsinchu County, Taiwan, and Wang, Yih, Hsinchu, Taiwan, for a “non-volatile memory device with reduced area.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode at one end. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode. The one end of the semiconductor fin is surrounded by the first gate electrode.”

The patent application was filed on 2021-04-16 (17/232639).

Memory with additional write bit lines
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11532351) developed by Fujiwara, Hidehiro, Huang, Chia-En, Chen, Yen-Huei, Hsinchu, Taiwan, Tsai, Jui-Che, Tainan, Taiwan, and Wang, Yih, Hsinchu, Taiwan, for a “memory device with additional write bit lines.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.”

The patent application was filed on 2020-05-08 (16/870030).

Method for programming memory
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11527289) developed by Lee, I-Che, Hsinchu, Taiwan, and Huang, Huai-Ying, Jhonghe, Taiwan, for a “method for programming memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.”

The patent application was filed on 2021-03-12 (17/199849).

Ferroelectric memory and method of forming
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11527552) developed by Lu, Chun-Chieh, Taipei, Taiwan, Yeong, Sai-Hooi, Zhubei, Lin, Yu-Ming, Hsinchu, Taiwan, Manfrini, Mauricio, Zhubei, Taiwan, and Vellianitis, Georgios, Heverlee, Belgium, for “ferroelectric memory device and method of forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.”

The patent application was filed on 2020-12-22 (17/130609).

Gated ferroelectric memory cells for memory cell array and methods of forming
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11515313) developed by Young, Bo-Feng, Taipei, Taiwan, Yeong, Sai-Hooi, Zhubei, Taiwan, Chia, Han-Jong, Wang, Sheng-Chen, and Lin, Yu-Ming, Hsinchu, Taiwan, for “gated ferroelectric memory cells for memory cell array and methods of forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.”

The patent application was filed on 2020-11-13 (17/096993).

Ferroelectric memory and method of forming
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11515332) developed by Lu, Chun-Chieh, Taipei, Taiwan, Yeong, Sai-Hooi, Zhubei, Taiwan, Young, Bo-Feng, Taipei, Taiwan, Lin, Yu-Ming, Hsinchu, Taiwan, and Chang, Chih-Yu, New Taipei, Taiwan, for “ferroelectric memory device and method of forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.”

The patent application was filed on 2020-12-01 (17/108218).

Memory and method for fabricating
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11515474) developed by Wu, Jung-Tang, Kaohsiung, Taiwan, Tung, Szu-Ping, Taipei, Taiwan, Wu, Szu-Hua, Pan, Shing-Chyang, Hsinchu County, Taiwan, and Wu, Meng-Yu, Taichung, Taiwan, for “memory device and method for fabricating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.”

The patent application was filed on 2020-12-04 (17/112861).

Embedded ferroelectric finFET memory
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11508753) developed by Young, Bo-Feng, Taipei, Taiwan, Lin, Chung-Te, Tainan, Taiwan, Yeong, Sai-Hooi, Zhubei, Taiwan, Lin, Yu-Ming, Hsinchu, Taiwan, Lai, Sheng-Chih, Hsinchu County, Taiwan, Chang, Chih-Yu, New Taipei, Taiwan, and Chia, Han-Jong, Hsinchu, Taiwan, for an “embedded ferroelectric finFET memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.”

The patent application was filed on 2020-02-24 (16/798719).

Memory circuit and write method
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11508427) developed by Wei, Huan-Sheng, Shen, Tzer-Min, and Wu, Zhiqiang, Hsinchu, Taiwan, for “memory circuit and write method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.”

The patent application was filed on 2021-03-11 (17/198790).

Stacked ferroelectric structure
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11508755) developed by Huang, Rainer Yen-Chieh, Chen, Hai-Ching, Hsinchu, Taiwan, and Lin, Chung-Te, Tainan, Taiwan, for a “stacked ferroelectric structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.”

The patent application was filed on 2021-02-25 (17/184856).

NVM and manufacturing technology
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, has been assigned a patent (11495743) developed by Hsu, Chern-Yow, Chu-Bei, Taiwan, Min, Chung-Chiang, Zhubei, Taiwan, and Liu, Shih-Chang, Alian Township, Taiwan, for “non-volatile memory device and manufacturing technology.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.”

The patent application was filed on 2020-05-05 (16/866704).