Sandisk Technologies/WD Assigned Twenty Patents

Multi-tier 3D memory device with dielectric support pillars and methods for making
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11495616) developed by Sakurai, Takuya, and Otsu, Yoshitaka, Yokkaichi, Japan, for “multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a semiconductor material layer, a memory opening and a support opening extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a semiconductor material portion in contact with the semiconductor material layer, and a support pillar structure located in the support opening. The support pillar structure lacks a semiconductor material portion which is in contact with the semiconductor material layer.”

The patent application was filed on 2020-09-04 (17/012862).

NVM with erase verify skip
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11495311) developed by Sanada, Kazuhiko, Kanagawa, Japan, for a “non-volatile memory with erase verify skip.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.”

The patent application was filed on 2021-06-25 (17/359208).

3D memory employing thinned insulating layers and methods for forming
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11489043) developed by Kai, James, Santa Clara, CA, Kanakamedala, Senaka, and Alsmeier, Johann, San Jose, CA, for “three-dimensional memory device employing thinned insulating layers and methods for forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.”

The patent application was filed on 2020-04-27 (16/859196).

Multi-tier 3D memory with nested contact via structures and methods for forming
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11488975) developed by Totoki, Yuji, and Amano, Fumitaka, Yokkaichi, Japan, for “multi-tier three-dimensional memory device with nested contact via structures and methods for forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces and located over a substrate, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces, and memory opening fill structures extending through the alternating stacks. A contact via assembly is provided, which includes a first conductive via structure vertically extending from a top surface of one of the first electrically conductive layers through a subset of layers within the second alternating stack and through the second retro-stepped dielectric material portion, an insulating spacer located within an opening through the subset of layers, and a second conductive via structure laterally surrounding the insulating spacer and contacting a second electrically conductive layer.”

The patent application was filed on 2020-10-27 (17/081458).

3-valued programming mechanism for NVM structures
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11488669) developed by Nose, Keiji, Yabe, Hiroki, Kano, Masahiro, and Fujita, Yuki, Kanagawa, Japan, for a “three-valued programming mechanism for non-volatile memory structures.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for programming three page user data in a memory array of a non-volatile memory system, comprising converting each three-bit value data pattern of the user data into a representative pair of two-bit data values, simultaneously programming two single- memory cells with a first of the pair of representative two-bit data values, wherein the two single- memory cells are located along a first common word line of two memory cell strings, and simultaneously programming two single- memory cells with a second of the pair of representative two-bit data values, wherein the two single- memory cells are located along a second common word line of the two memory cell strings.”

The patent application was filed on 2020-12-29 (17/136828).

Dynamic re-evaluation of parameters for NVM using microcontroller
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11487548) developed by Chinchole, Vijay, Padattil Kuliyampattil, Nisha, Agarwal, Sonam, Agarwal, Akash, Devaraj, Pavithra, Karnataka, India, and Li, Yan, Milpitas, CA, for a “dynamic re-evaluation of parameters for non-volatile memory using microcontroller.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.”

The patent application was filed on 2019-11-26 (16/695759).

Per Pin Vref for data receivers in NVM system
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11482262) developed by Lee, Jang Woo, Seongnam-si, Korea, Rajendra, Srinivas, Milpitas, CA, Pai, Anil, and Ramachandra, Venkatesh, San Jose, CA, for a “per Pin Vref for data receivers in non-volatile memory system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Technology is disclosed herein for per pin internal reference voltage generation for data receivers in non-volatile memory systems. A receiving circuit may have an on-die voltage generator that has inputs to receive a separate voltage magnitude select signal for each data receiver on the receiving circuit. The on-die voltage generator provides a separate reference voltage for each data receiver. This allows the reference voltage for each data receiver to be calibrated separately. A separate reference voltage for each data receiver compensates for variations between data paths, and provides for a wider data valid window than if the same reference voltage were used for all data receivers. Generating the different reference voltages on-die can potentially require a large area, as well as consume considerable power and/or current. A voltage divider and multiplexers may provide the different reference voltages, which saves space and is power and current efficient.”

The patent application was filed on 2021-06-16 (17/348904).

NVM with memory array between circuits
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11481154) developed by Dutta, Deepanshu, Fremont, CA, Kai, James, Santa Clara, CA, Alsmeier, Johann, and Chen, Jian, San Jose, CA, for a “non-volatile memory with memory array between circuits.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.”

The patent application was filed on 2021-01-15 (17/149867).

Application based verify level offsets for NVM
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11482289) developed by Prakash, Abhijith, Milpitas, CA, and Khandelwal, Anubhav, San Jose, CA, for an “application based verify level offsets for non-volatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory apparatus and method of operation are provided. The apparatus includes a plurality of memory cells. Each of the plurality of memory cells is connected to one of a plurality of word lines and is arranged in one of a plurality of blocks. Each of the plurality of memory cells is configured to retain a threshold voltage corresponding to one of a plurality of data s. A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation.”

The patent application was filed on 2021-03-04 (17/192090).

3D memory including metal silicide source regions and methods for forming
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11482539) developed by Sharangpani, Rahul, Fremont, CA, Makala, Raghuveer S., Campbell, CA, Zhou, Fei, San Jose, CA, and Rajashekhar, Adarsh, Santa Clara, CA, for “three-dimensional memory device including metal silicide source regions and methods for forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.”

The patent application was filed on 2020-10-28 (17/082629).

3D memory including multi-bit charge storage elements and methods for forming
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11482531) developed by Said, Ramy Nashed Bassely, San Jose, CA, Yuan, Jiahui, Fremont, CA, Kanakamedala, Senaka, San Jose, CA, Makala, Raghuveer S., Campbell, CA, and Lee, Dana, San Jose, CA, for “three-dimensional memory device including multi-bit charge storage elements and methods for forming the Same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.”

The patent application was filed on 2021-02-08 (17/169987).

NVM with efficient look-ahead read
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11475961) developed by Islam, Sujjatul, San Jose, CA, Kumar, Ravi J., Redwood , CA, and Dutta, Deepanshu, Fremont, CA, for a “nonvolatile memory with efficient look-ahead read.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased condition. The one or more control circuits are further configured to determine a read voltage to read non-volatile memory cells of a corresponding target word line according to an amount of charge in non-volatile memory cells of the selected neighboring word line.”

The patent application was filed on 2021-05-04 (17/307396).

3D memory with graphene channel and methods of making
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11476272) developed by Rabkin, Peter, and Higashitani, Masaaki, Cupertino, CA, for “three-dimensional memory device with a graphene channel and methods of making the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Each memory stack structure includes a memory film and a vertical semiconductor channel. A sacrificial polycrystalline metal layer may be formed on each memory film, and a carbon precursor may be decomposed on a physically exposed surface of the sacrificial polycrystalline metal layer to generate adsorbed carbon atoms. A subset of the adsorbed carbon atoms diffuses through grain boundaries in the polycrystalline e metal layer to an interface with the memory film. The carbon atoms at the interface may be coalesced into at least one graphene layer by an anneal process. The at least one graphene layer functions as a vertical semiconductor channel, which provides a higher mobility than silicon. A metallic drain region may be formed at an upper end of each vertical semiconductor channel.”

The patent application was filed on 2018-12-20 (16/227374).

Optimized programming with single bit per memory cell and multiple bits per memory cell
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11475957) developed by Zainuddin, Abu Naser, Milpitas, CA, Liao, Dongxiang, Sunnyvale, CA, and Yuan, Jiahui, Fremont, CA, for “optimized programming with a single bit per memory cell and multiple bits per memory cell.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Apparatuses and techniques are described for optimizing programming in a memory device in which memory cells can be programmed using single bit per cell programming and multiple bits per cell programming. In one aspect, a single bit per cell program operation is performed which reduces damage to the memory cells as well as reducing program time. The program operation can omit a pre-charge phase and a verify phase of an initial program loop of a program operation. Instead, a program phase is performed followed by a recovery phase. In one or more subsequent program loops of the single bit per cell program operation, as well as in each program loop of a multiple bit per cell program operation, the program loop includes a pre-charge phase, a program phase, a recovery phase and a verify phase.”

The patent application was filed on 2021-01-14 (17/149560).

Memory using multilayer ferroelectric stack and method of forming
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11469251) developed by Zhang, Yanli, and Alsmeier, Johann, San Jose, CA, for “memory device using a multilayer ferroelectric stack and method of forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.”

The patent application was filed on 2019-05-15 (16/412764).

3D memory including discrete charge storage elements and methods of forming
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11469241) developed by Makala, Raghuveer S., Campbell, CA, Kanakamedala, Senaka, Zhou, Fei, San Jose, CA, and Lee, Yao-Sheng, Tampa, FL, for “three-dimensional memory device including discrete charge storage elements and methods of forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.”

The patent application was filed on 2020-04-15 (16/849664).

Reverse VT- operation and optimized bics device structure
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11456044) developed by Sakakibara, Kiyohiko, Mie, Japan, for “reverse VT- operation and optimized bics device structure.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data s of the memory cell transistors may be reversed such that the erased comprises the highest data corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data s, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon.”

The patent application was filed on 2021-03-11 (17/199245).

3D memory containing bridges for enhanced structural support and methods of forming
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11450685) developed by Yoshida, Yusuke, Yokkaichi, Japan, for “three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.”

The patent application was filed on 2021-02-11 (17/174094).

Multibit ferroelectric memory cells and methods for forming
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11450687) developed by Tirukkonda, Roshan, Milpitas, CA, Said, Ramy Nashed Bassely, Kanakamedala, Senaka, San Jose, CA, Sharangpani, Rahul, Fremont, CA, Makala, Raghuveer S., Campbell, CA, Rajashekhar, Adarsh, Santa Clara, CA, and Zhou, Fei, San Jose, CA, for “multibit ferroelectric memory cells and methods for forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.”

The patent application was filed on 2020-12-15 (17/122360).

3D memory including stairless word line contact structures for and method of making
Sandisk Technologies LLC, a Western Digital Corp. brand, Addison, TX, has been assigned a patent (11450679) developed by Tanaka, Yoshinobu, Ito, Koichi, Hasegawa, Hideaki, Tobioka, Akihiro, and Lee, Sung Tae, Yokkaichi, Japan, for “three-dimensional memory device including stairless word line contact structures for and method of making the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.”

The patent application was filed on 2020-07-01 (16/918493).