Ememory Technology Assigned Seven Patents

NVM with multi-level cell array and associated program control method
Ememory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11557338) developed by Chang, Chia-Fu, Ku, Wei-Ming, and Chen, Ying-Je, Hsinchu County, Taiwan, for “non-volatile memory with multi-level cell array and associated program control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit, a verification circuit and a control circuit. During a sample period of a verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the verification circuit and convert the n M-th reference currents into n reference voltages. During a verification period of the verification action, the control circuit controls n multi-level memory cells of a selected row of the cell array to generate n cell currents to the verification circuit and convert the n cell currents into n sensed voltages. The n verification devices generate the n verification signals according to the reference voltages and the sensed voltages. Accordingly, the control circuit judges whether the n multi-level memory cells have reached an M-th storage state.”

The patent application was filed on 2021-05-13 (17/319127).

Memory and method for operating
Ememory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11551738) developed by Hsu, Chia-Jung, Chen, Wei-Ren, and Sun, Wein-Town, Hsinchu County, Taiwan, for “memory device and method for operating memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a well, a poly layer, a dielectric layer, an alignment layer and an active area. The poly layer is formed above the well. The dielectric layer is formed above the poly layer. The alignment layer is formed on the dielectric layer, used to receive an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction. The active area is formed on the well. The dielectric layer is thicker than the alignment layer. A first overlap area of the poly layer and the active area is smaller than a second overlap area of the poly layer and the dielectric layer excluding the first overlap area.”

The patent application was filed on 2021-04-08 (17/225116).

Read-only memory cell and associated memory cell array
Ememory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11521980) developed by Sun, Wein-Town, Hsinchu County, Taiwan, for “read-only memory cell and associated memory cell array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A read-only memory cell array includes a first storage memory cell and a second storage memory cell. The first storage memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.”

The patent application was filed on 2020-09-22 (17/027750).

Memory including alignment layer and semiconductor process method
Ememory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11508720) developed by Hsu, Chia-Jung, Chen, Wei-Ren, and Sun, Wein-Town, Hsinchu County, Taiwan, for “memory device including alignment layer and semiconductor process method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.”

The patent application was filed on 2020-05-12 (16/872380).

Memory cell array of programmable NVM
Ememory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11508425) developed by Hsu, Chia-Jung, and Sun, Wein-Town, Hsinchu County, Taiwan, for a “memory cell array of programmable non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell of a memory cell array includes a well region, a first doped region, a second doped region, a first gate structure, and a storage structure. The first doped region and the second doped region are formed in the well region. The first gate structure is formed over a first surface between the first doped region and the second doped region. The storage structure is formed over a second surface and the second surface is between the first surface and the second doped region. The storage structure is covered on a portion of the first gate structure, the second surface and an isolation structure.”

The patent application was filed on 2021-02-09 (17/170946).

Memory capable of improving erase and program efficiency
Ememory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11502096) developed by Hsu, Chia-Jung, and Sun, Wein-Town, Hsinchu County, Taiwan, for “memory device capable of improving erase and program efficiency.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well.”

The patent application was filed on 2021-08-04 (17/393413).

Random code generator and associated random code generating
Ememory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11404958) developed by Hsu, Ching-Hsiang, Hsinchu County, Taiwan, for “random code generator and associated random code generating method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A random code generator includes a power source, a sensing circuit, a first memory cell and a second memory cell. A first terminal of the first memory cell is connected with the power source. A second terminal of the first memory cell is connected with the sensing circuit. A first terminal of the second memory cell is connected with the power source. A second terminal of the second memory cell is connected with the sensing circuit. The power source provides a supplying voltage to both the first memory cell and the second memory cell during an enrollment. A random code is then determined according to the resistance difference between the first memory cell and the second memory cell after the enrollment.”

The patent application was filed on 2019-05-24 (16/421820).