Radian Memory Systems Assigned Seven Patents

NVM controller host-issued address delimited erasure and memory controller remapping of host-address space for bad blocks
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11544183) developed by Kuzmin; Andrey V., Moscow, Russia, Jadon; Mike, Manhattan Beach, CA, and Mathews; Richard M., Chatsworth, CA, for “nonvolatile memory controller host-issued address delimited erasure and memory controller remapping of host-address space for bad blocks.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.”

The patent application was filed on 2020-08-19 (16/997471).

Storage drive with NAND maintenance on basis of segments corresponding to logical erase units
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11544200) developed by Lercari; Robert, Thousand Oaks, CA, Chen; Alan, Simi Valley, CA, Jadon; Mike, Manhattan Beach, CA, Robertson; Craig, Simi Valley, CA, and Kuzmin; Andrey V., Moscow, Russia, for a “storage drive with NAND maintenance on basis of segments corresponding to logical erase units.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on 2022-09-01 (17/901584).

Storage system with division based addressing and query based cooperative flash management
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11537528) developed by Lercari; Robert, Thousand Oaks, CA, Chen; Alan, Simi Valley, CA, Jadon; Mike, Manhattan Beach, CA, Robertson; Craig, Simi Valley, CA, and Kuzmin; Andrey V., Moscow, Russia, for a “storage system with division based addressing and query based cooperative flash management.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on 2021-12-27 (17/562873).

Storage drive with defect management on basis of segments corresponding to logical erase units
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11537529) developed by Lercari; Robert, Thousand Oaks, CA, Chen; Alan, Simi Valley, CA, Jadon; Mike, Manhattan Beach, CA, Robertson; Craig, Simi Valley, CA, and Kuzmin; Andrey V., Moscow, Russia, for a “storage drive with defect management on basis of segments corresponding to logical erase units.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on 2022-09-01 (17/901557).

Techniques for directed data migration
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11481144) developed by Chen; Alan, Robertson; Craig, Simi Valley, CA, Lercari; Robert, Thousand Oaks, CA, and Kuzmin; Andrey V., Moscow, Russia, for “techniques for directed data migration.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A host stores ‘context’ metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.”

The patent application was filed on 2021-02-15 (17/176035).

Techniques for supporting erasure coding with flash memory controller
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11449240) developed by Jadon; Mike, Manhattan Beach, CA, Robertson; Craig, Simi Valley, CA, and Lercari; Robert, Thousand Oaks, CA, for “techniques for supporting erasure coding with flash memory controller.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.”

The patent application was filed on 2021-04-26 (17/240788).

Maintenance of NVM on host selected namespaces by common memory controller
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11249652) developed by Kuzmin; Andrey V., Moscow, Russia, Chen; Alan, Simi Valley, CA, and Lercari; Robert, Thousand Oaks, CA, for a “maintenance of nonvolatile memory on host selected namespaces by a common memory controller.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.”

The patent application was filed on 2020-03-27 (16/832793).