Kioxia Assigned Fourteen Patents

Resistive random access memory device with 3D cross-point structure and method of operating
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11495292) developed by Sugimae, Kikuko, and Arayashiki, Yusuke, Mie, Japan, for a “resistive random access memory device with three-dimensional cross-point structure and method of operating the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.”

The patent application was filed on 2021-03-09 (17/195994).

Memory system with accessible storage region to gateway
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11494104) developed by Yamazaki, Atsushi, Hachioji Tokyo, Japan, Umesawa, Kentaro, Kawasaki Kanagawa, Japan, Yamada, Naoko, and Kageyama, Yuta, Yokohama Kanagawa, Japan, for a “memory system with accessible storage region to gateway.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system comprising a first storage region which stores first firmware corresponding to an external first electronic control apparatus, a second storage region which stores second firmware corresponding to an external gateway and third firmware corresponding to the first electronic control apparatus, and a controller configured to transmit the second firmware and the third firmware to the gateway on the basis of a first command received from the gateway, and transmit the first firmware to the gateway on the basis of a second command received from the gateway.”

The patent application was filed on 2019-07-30 (16/526591).

Memory system and control method
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11494123) developed by Kanamori, Katsuya, and Fujita, Takafumi, Yokohama Kanagawa, Japan, for “memory system and control method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system includes a non-volatile memory, and a controller configured to issue a first command requesting a first operation to the non-volatile memory and a second command to the non-volatile memory. The second command may be for requesting a duration time of the first operation or for requesting an execution stage of the first operation. In accordance with the information returned by the non-volatile memory in response to the second command, the controller issues a third command requesting a completion status of the first operation to the non-volatile memory. The first operation may be a data read operation, a data write operation, or a data erase operation.”

The patent application was filed on 2021-01-15 (17/150991).

Memory system with selective access to first and second memories
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11494077) developed by Nagadomi, Yasushi, Kanagawa, Japan, for a “memory system with selective access to first and second memories.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.”

The patent application was filed on 2021-03-19 (17/207021).

Variable resistance memory
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11495295) developed by Asao, Yoshiaki, Kawasaki Kanagawa, Japan, for a “variable resistance memory device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A variable resistance memory device includes: a memory cell including a first and second sub memory cell, and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell.”

The patent application was filed on 2021-06-16 (17/349162).

NVM having resistance change memory element and switching element portions serially connected thereto
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11495636) developed by Kumura, Yoshinori, Seoul, Korea, for a “nonvolatile memory device having a resistance change memory element and switching element portions serially connected thereto.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a nonvolatile memory device includes a plurality of wiring line pairs each including a pair of first and second wiring lines extending in a first direction, a plurality of third wiring lines each extending in a second direction intersecting the first direction, and a plurality of memory cells provided between the wiring line pairs and the third wiring lines. Each of the memory cells includes a resistance change memory element connected to the third wiring line, and a switching element structure including a first switching element portion provided between the resistance change memory element and the first wiring line, and a second switching element portion provided between the resistance change memory element and the second wiring line.”

The patent application was filed on 2020-03-12 (16/817078).

Switch and memory device
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (RE49273) developed by Yamaguchi, Takashi, Yokohama, Japan, Yoshida, Norikazu, Kawasaki, Japan, and Anazawa, Mitsuru, Sagamihara, Japan, for “switch and memory device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.”

The patent application was filed on 2020-09-04 (17/012714).

Non-volatile semiconductor storage device
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (RE49274) developed by Nakamura, Dai, Kawasaki, Japan, Kutsukake, Hiroyuki, Yokohama, Japan, Gomikawa, Kenji, Yokohama, Japan, Shimane, Takeshi, Matsudo, Japan, Noguchi, Mitsuhiro, Yokohama, Japan, Hosono, Koji, Fujisawa, Japan, Koyanagi, Masaru, Ota, Japan, and Aoi, Takashi, Yokohama, Japan, for a “non-volatile semiconductor storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner, and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film, and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.”

The patent application was filed on 2019-02-25 (16/284203).

Memory system and method of fetching command
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11487477) developed by Katagiri, Toru, Sagamihara Kanagawa, Japan, for “memory system and method of fetching command.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system includes a non-volatile memory and a controller. The controller controls writing of data to the non-volatile memory or reading of data from the non-volatile memory, in response to a command from at least one host. The controller performs command fetching by calculating for each of a plurality of queues, a remaining processing amount, which is an amount of processing remaining for one or more commands previously fetched therefrom, selecting a queue based on the remaining processing amounts calculated for the plurality of queues, and fetching a new command from the selected queue.”

The patent application was filed on 2021-02-26 (17/186478).

Semiconductor storage device, method of controlling, and memory system
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11486767) developed by Terada, Keisuke, Kamakura Kanagawa, Japan, and Takahashi, Eietsu, Yokohama Kanagawa, Japan, for “semiconductor storage device, method of controlling semiconductor storage device, and memory system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device includes a memory cell and a control circuit configured to, upon receipt of a command, acquire a first temperature measured by a temperature sensor, and perform an operation corresponding to the command using a parameter corrected based on temperature. When the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature. When the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.”

The patent application was filed on 2021-03-01 (17/189140).

Memory system and method of controlling NVM
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11487478) developed by Kanno, Shinichi, Ota, Japan, for “memory system and method of controlling nonvolatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.”

The patent application was filed on 2021-03-16 (17/202704).

Semiconductor storage device and method of manufacturing
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11488972) developed by Oshima, Yasunori, Yokkaichi, Japan, for “semiconductor storage device and method of manufacturing the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one embodiment, a semiconductor storage device includes a substrate, a stacked film including a plurality of first insulating layers and a plurality of electrode layers that are alternately provided on the substrate, and a second insulating layer provided on the stacked film. The device further includes a plurality of pillar portions, each of which including a first insulator, a charge storage layer, a second insulator, a first semiconductor layer and a third insulator that are sequentially provided in the stacked film and the second insulating layer. Furthermore, a width of the second insulating layer sandwiched between the pillar portions is narrower than a width of the stacked film sandwiched between the pillar portions, in at least a portion of the second insulating layer.”

The patent application was filed on 2020-03-05 (16/809753).

Semiconductor storage device including first pads on first chip that are bonded to second pads on second chip
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11482514) developed by Harashima, Hiromitsu, Yokohama Kanagawa, Japan, and Kameda, Yasushi, Hayama Kanagawa, Japan, for a “semiconductor storage device including first pads on a first chip that are bonded to second pads on a second chip.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other.”

The patent application was filed on 2020-02-27 (16/803485).

Payload spill boundary table assisted read in solid drives
Kioxia Corp.,Tokyo, Japan, has been assigned a patent (11481151) developed by Jain, Amit, Cupertino, CA, Prakash, Gyan, San Jose, CA, and Puttaswamy, Ashwini, Cupertino, CA, for a “payload spill boundary table assisted read in solid drives.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method performed by a controller of a solid drive comprising receiving from a host a read request for read data stored in nonvolatile semiconductor storage devices of the solid drive. The method also comprises identifying a first codeword and a second codeword, the first codeword and the second codeword comprising the read data corresponding to the read request. Responsive to the read request, the method comprises reading a first portion of the read data contained in the first codeword and reading a second portion of the read data contained in the second codeword, assembling the first portion and the second portion as assembled read data, and transferring the assembled read data to the host responsive to the read request. The first and second codewords are adjacently stored, and the assembled read data has a length that is greater than the length of the first and second codewords.”

The patent application was filed on 2020-07-17 (16/932038).