Macronix International Assigned Fifteen Patents

3D memory device with increased memory cell density
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11538827) developed by Lee, Chih-Hsiung, Hsinchu, Taiwan, for a “three-dimensional memory device with increased memory cell density.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device and method of forming the same are provided. The memory device includes a word line, a bit line, a source line, a channel pillar, and a charge storage structure. The bit line and the source line are disposed on opposite sides of the word line in a vertical direction. The channel pillar penetrates through and is connected to the word line, the bit line and the source line. The charge storage structure surrounds a top surface and a bottom surface of the word line and is laterally sandwiched between the channel pillar and the word line. The channel pillar completely penetrates through and is laterally surrounded by the bit line.”

The patent application was filed on 2020-07-23 (16/937340).

3D NAND flash memory and method of fabricating
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11521898) developed by Hung, Min-Feng, Hsing-Chu, Taiwan, for “three-dimensional NAND flash memory device and method of fabricating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device is provided. The memory device includes a substrate, a stacked structure, and a contact. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on each other. Each of the plurality of conductive layers includes a main body and an end part. The main body is located in the memory array region and extends to the staircase region. The end part is connected to the main body and is located in the staircase region. A thickness of the end part is greater than a thickness of the main body. The contact lands on and is connected to the end part.”

The patent application was filed on 2020-11-12 (17/096539).

Memory device and control method
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11501841) developed by Chen, Chung-Kuang, Hsinchu, Taiwan, for “memory device and control method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a memory cell array, a current detector and a controller. The memory cell array has a plurality of memory cell strings coupled to a common source line. The current detector detects a circulating current on the common source line or a power end of a page buffer. The controller is configured to: during a program operation, perform a first program operation on a plurality of first memory cells corresponding to logic 0 according to a first program verify voltage, and perform a second program operation on a plurality of second memory cells corresponding to logic 1 according to a second program verify voltage, where the first program verify voltage is different from the second program verify voltage, and provide a read voltage to the memory cell strings during a read operation, and sense the circulating current based on a read current reference value.”

The patent application was filed on 2021-02-08 (17/169919).

File system management in memory device
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11500775) developed by Su, Chun-Lien, Taichung, Taiwan, for a “file system management in memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system stores user data including file content in clusters of memory space, folder entries, metadata, and a file allocation table FAT including FAT entries. The system comprises a cache memory, an addressable memory including memory space, and control logic coupled to the addressable memory and the cache memory. The control logic is configured to store user data in a current cluster at a current cluster offset including file content, and corresponding metadata including the current cluster offset, and a linked cluster offset of a linked cluster linking to the current cluster in the addressable memory, and to cache a FAT entry pointing to the current cluster in the cache memory.”

The patent application was filed on 2021-02-24 (17/184352).

3D memory device and ternary content addressable memory cell
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11495298) developed by Hsu, Po-Kai, Tainan, Taiwan, Yeh, Teng-Hao, Hsinchu County, Taiwan, and Lue, Hang-Ting, Hsinchu, Taiwan, for “three dimension memory device and ternary content addressable memory cell thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three dimension memory device and a ternary content addressable memory cell are provided. The ternary content addressable memory cell includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND type flash memory line. The second memory cell is disposed in a second AND type flash memory line. The first search switch is coupled between a first bit line corresponding to the first AND type flash memory line and a match line, and is controlled by a first search signal to be turned on or cut off. The second search switch is coupled between a second bit line corresponding to the second AND type flash memory line and the match line, and is controlled by a second search signal to be turned on or cut off.”

The patent application was filed on 2021-09-02 (17/465651).

Fast interval read setup for 3D NAND flash
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11475954) developed by Chen, Han-Sung, and Chen, Chung-Kuang, Hsinchu, Taiwan, for a “fast interval read setup for 3D NAND flash.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.”

The patent application was filed on 2021-01-20 (17/153525).

3D flash memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11476273) developed by Lue, Hang-Ting, Hsinchu, Taiwan, for a “three-dimensional flash memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Provided are various three-dimensional flash memory devices. A three-dimensional flash memory device includes a gate stacked structure, separate arc-shaped channel pillars, source/drain pillars and a charge storage structure. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The arc-shaped channel pillar are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate and penetrate through the gate stacked structure, wherein two source/drain pillars are disposed at two ends of each of the arc-shaped channel pillars. The charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel pillar.”

The patent application was filed on 2020-07-08 (16/924001).

Flash memory system and device
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11455254) developed by Su, Chun-Lien, Taichung, Taiwan, Hung, Chun-Hsiung, Hsinchu, Taiwan, and Hung, Shuo-Nan, Hsinchu County, Taiwan, for “flash memory system and flash memory device thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer, and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.”

The patent application was filed on 2020-12-10 (17/118239).

Flash memory and method of fabricating
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11,417,683) developed by Lue, Hang-Ting, Hsinchu, Taiwan, for “flash memory and method of fabricating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Provided is a flash memory includes a gate stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, and a gate dielectric layer. The gate stack structure includes a plurality of gate layers electrically insulated from each other. Each gate layer includes a ferroelectric portion disposed between a sidewall of a first portion and a sidewall of a second gate portion. A thickness of the second gate portion is smaller than a thickness of the first gate portion. A channel pillar penetrates the gate stack structure. The first and second conductive pillars are disposed in the channel pillar. The first and second conductive pillars are separated from each other, and are each connected to the channel pillar. The gate dielectric layer is disposed between another sidewall of the first gate portion and the channel pillar.”

The patent application was filed on October 22, 2020 (17/077,847).

Implementing read setup in 3D NAND flash memory to reduce voltage threshold deviation over time
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11,385,839) developed by Chung, Chin-Chu, Liu, Chien-Hsin, and Yeh, Yu-Chih, Hsinchu, Taiwan, for “implementing a read setup in 3D NAND flash memory to reduce voltage threshold deviation over time.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of operating a memory is provided. The method includes, in response to an access of a block of memory updating a first queue to identify the accessed block in response to a determination that the block is not already identified in the first queue and a determination that the block is not already identified in a second queue, and updating the second queue to identify the accessed block of memory in response to a determination that the block is already identified in the first queue. The method further includes scanning the second queue to identify, as a read setup candidate, each block of the memory that is identified as present in the second queue longer than a threshold, and performing a read setup operation on a block of memory that has been identified as the read setup candidate.”

The patent application was filed on April 27, 2021 (17/242,123).

3D memory including source line structure comprising composite material
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11,374,099) developed by Liao, Ting-Feng, Hsinchu, Taiwan, Chen, Sheng-Hong, Kaohsiung, Taiwan, and Liu, Kuang-Wen, Hsinchu, Taiwan, for a “3D memory device including source line structure comprising composite material.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.”

The patent application was filed on July 16, 2020 (16/930,505).

High thermal stability SiO.sub.x doped GeSbTe materials suitable for embedded PCM application
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11,362,276) developed by Cheng, Huai-Yu, White Plains, NY, and Lung, Hsiang-Lan, Ardsley, NY, for “high thermal stability SiO.sub.x doped GeSbTe materials suitable for embedded PCM application.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A phase-change material having specific SiO.sub.x doping into special Ge-rich Ge.sub.xSb.sub.yTe.sub.z material is described. Integrated circuits using this phase-change material as memory elements in a memory array can pass the solder bonding criteria mentioned above, while exhibiting good set speeds and demonstrating good 10 year data retention characteristics. A memory cell described herein comprises a first electrode and a second electrode, and a memory element in electrical series between the first and second electrode. The memory element comprises a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %.”

The patent application was filed on March 27, 2020 (16/833,349).

3D memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11,362,101) developed by Chiu, Chien-Lan, Yunlin County, Taiwan, and Cheng, Chun-Min, Hsinchu, Taiwan, for a “three dimensional memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure on a first region of a semiconductor substrate. The multi-layer stacked structure includes a stair structure and a non-stair structure. A plurality of memory structures are located in the non-stair structure to form a memory array region, and each memory structure passes through the conductive layers and the insulating layers. A plurality of bow-height adjustment features are located in a second region of the semiconductor substrate.”

The patent application was filed on March 5, 2020 (16/809,719).

Inference operation method and controlling circuit of 3D NAND AI
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11,309,028) developed by Hsu, Po-Kai, Tainan, Taiwan, and Yeh, Teng-Hao, Zhubei, Taiwan, for “inference operation method and controlling circuit of 3D NAND artificial intelligence.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An inference operation method and a controlling circuit of a 3D NAND artificial intelligence accelerator are provided. The 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line. The inference operation method includes the following steps: The patterns are inputted to the bit lines. The word lines are switched to switch the filters. The string selecting line groups are switched to switch the filters. In a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched.”

The patent application was filed on September 3, 2020 (17/011,039).

Flash memory device and control
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (11,270,755) developed by Chen, Chung-Kuang, Hsinchu, Taiwan , for “flash memory device and control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell strings respectively have a plurality of string selecting switches, wherein the plurality of string selecting switches are controlled by a string selecting control voltage. The string selecting control voltage generator is coupled to the memory cell strings, and generate the string selecting control voltage according to an ambient temperature during a writing operation performed on the plurality of memory cell strings. Wherein each of the plurality of memory cell strings is inhibited, programmed or quick pass written during the writing operation.”

The patent application was filed on December 23, 2020 (17/132,999).