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Kioxia Assigned Fifteen Patents

Controlling memory system, media error reporting improvements for storage drives, NVM having at least one metal body and one semiconductor body extending through electrode stack, magnetoresistive memory, storage device that writes data from host during garbage collection, metadata management in NVM devices using in-memory journal, memory system and method for controlling NVM, memory device, host device, system, memory device control, host device control and memory system control method, NVM controlling partical usage restriction for memory cell array, NVM that stores temperature information therein, magnetic storage, controlling RW operations in NVM by host, using identifier for region

Controlling memory system
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11482287) developed by Komatsu, Yuki, Kawasaki Kanagawa, Japan, and Shimada, Katsuyuki, Ota Tokyo, Japan, for “memory system and method of controlling memory system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system includes a memory and a controller. The memory includes at least a first memory cell and a second memory cell. The controller can determine a first stress type that the first memory cell received or a second stress type that the second memory cell received based on a change amount between a first read threshold voltage to read data from the first memory cell when having received stress, and a second read threshold voltage to read data from the first memory cell when having received no stress.

The patent application was filed on 2021-03-03 (17/191331).

Media error reporting improvements for storage drives
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11482294) developed by Buxton, Neil, Berkshire, Great Britain, Asano, Shigehiro, Tokyo, Japan, Wells, Steven, Rancho Cordova, CA, and Carlson, Mark, Longmont, CO, for “media error reporting improvements for storage drives.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.

The patent application was filed on 2021-06-01 (17/335546).

NVM having at least one metal body and one semiconductor body extending through electrode stack
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11482537) developed by Tsuji, Masaki, and Fukuzumi, Yoshiaki, Yokkaichi, Japan, for a non-volatile memory device having at least one metal body and one semiconductor body extending through the electrode stack.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

The patent application was filed on 2020-07-28 (16/940472).

Magnetoresistive memory
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11475931) developed by Tsubata, Shuichi, Kuwana Mie, Japan, and Akiyama, Naoki, Seoul, Korea, for a magnetoresistive memory device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a magnetoresistive memory device includes: a first conductor, a layer stack, an insulator on a side surface of the layer stack, a second conductor on a second surface of the layer stack, a third conductor, and a fourth conductor on the third conductor. The layer stack includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer and has a first surface in contact with the first conductor. The second surface is at an opposite side of the first surface. The third conductor has a portion on the second conductor and a portion on a side surface of the insulator.

The patent application was filed on 2020-09-09 (17/016212).

Storage device that writes data from host during garbage collection
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11474702) developed by Kanno, Shinichi, Ota Tokyo, Japan, for a storage device that writes data from a host during garbage collection.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.

The patent application was filed on 2020-07-27 (16/940269).

Metadata management in NVM devices using in-memory journal
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11467970) developed by Tomlin, Andrew John, San Jose, CA, for a metadata management in non-volatile memory devices using in-memory journal.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Various implementations described herein relate to systems and methods for managing metadata for an atomic write operation, including determining metadata for data, queuing the metadata in an atomic list, in response to determining that atomic commit has occurred, moving the metadata from the atomic list to write lookup lists based on logical information of the data, and determining one of metadata pages of a non-volatile memory for each of the write lookup lists based on the logical information.

The patent application was filed on 2021-08-03 (17/393087).

Memory system and method for controlling NVM
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11467955) developed by Kanno, Shinichi, Tokyo, Japan, for memory system and method for controlling nonvolatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

The patent application was filed on 2021-04-27 (17/241492).

Memory system
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11468159) developed by Numata, Kenichi, Kokubunji Tokyo, Japan, and Tarui, Sachi, Yokohama Kanagawa, Japan, for a memory system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system includes a nonvolatile memory including user areas, a volatile memory, a battery, and a controller configured to, when the volatile memory maintains first information indicating an access to a user area is permitted and a verification value upon startup of the system, determine whether the information is validated by the value, and upon determining that the information is validated, permit an access to the user area and prohibit the access to any other area, and when the volatile memory does not maintain the information and value, or the information is not validated, prohibit an access to any user area, and thereafter, upon receipt of a command and authentication information from the host, permit an access to the user area requested by the command, and generate and store in the volatile memory the information and the value for validating the generated information.

The patent application was filed on 2020-03-03 (16/808186).

Memory device, host device, system, memory device control, host device control and memory system control method
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (RE49235) developed by Fujimoto, Akihisa, Kanagawa, Japan, for memory device, host device, memory system, memory device control method, host device control method and memory system control method.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.

The patent application was filed on 2020-12-28 (17/135608).

NVM controlling partical usage restriction for memory cell array
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11461044) developed by Hiraishi, Tomoya, Yokohama, Japan, for a nonvolatile memory device controlling partical usage restriction for memory cell array.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a nonvolatile memory device includes a memory cell array, first and second storage units, and control unit. The memory cell array includes erase unit areas. The first storage units correspond respectively to the erase unit areas and store items of first information indicating whether a first usage restriction is to be imposed on the corresponding erase unit areas. The second storage units correspond respectively to the erase unit areas and store items of second information indicating whether a second usage restriction is to be imposed on the corresponding erase unit areas. The control unit executes switching control on whether the first usage restriction is to be imposed or not and whether the second usage restriction is to be imposed or not on the memory cell array based on the first and second information.

The patent application was filed on 2018-09-10 (16/126134).

NVM that stores temperature information therein
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11461039) developed by Kurosawa, Yasuhiko, Fujisawa Kanagawa, Japan, for a nonvolatile memory that stores temperature information therein.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A nonvolatile memory includes a memory array, a sensor for measuring a temperature, an interface through which a write command is to be received, and a control circuit. The control circuit is configured to write information of the temperature measured by the sensor in a data storing area of the memory array in which user data associated with the write command is not capable of being written into, when writing the user data in the memory array in response to the received write command.

The patent application was filed on 2019-08-28 (16/554381).

Magnetic storage
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11462680) developed by Watanabe, Daisuke, Yokkaichi Mie, Japan, and Nagase, Toshihiko, Kuwana Mie, Japan, for a magnetic storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A magnetic storage device includes a magnetoresistive effect element. The magnetoresistive effect element includes a first ferromagnetic layer, a second ferromagnetic layer, a non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer, and a first layer provided at a side of the first ferromagnetic layer opposite to a side of the first ferromagnetic layer at which the non-magnetic layer is provided. The first layer includes a rare-earth element and the first layer has a region including boron (B) at a proportion higher than a proportion of boron (B) in the first ferromagnetic layer.

The patent application was filed on 2021-02-22 (17/181087).

Memory system
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11462256) developed by Asami, Shohei, Fujisawa, Japan, Hida, Toshikatsu, and Suzuki, Riki, Yokohama, Japan, for a memory system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.

The patent application was filed on 2021-06-16 (17/349248).

Controlling WR operations in NVM by host, using identifier for region
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11461049) developed by Kanno, Shinichi, Ota, Japan, for a method for controlling write and read operations in the nonvolatile memory by a host, using an identifier for a region.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.

The patent application was filed on 2021-01-08 (17/144641).

Storage device
Kioxia
Corp.,Tokyo, Japan, has been assigned a patent (11455115) developed by Futagi, Junpei, Yokohama, Japan, and Umesawa, Kentaro, Kawasaki, Japan, for a storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to control data write to the nonvolatile memory and data read from the nonvolatile memory based on a command from a host. The controller includes at least one processor. The nonvolatile memory stores first firmware for normal operation and second firmware for recovery. The first firmware is firmware to cause the at least one processor to control the data write and the data read based on the command. The second firmware is firmware to cause the at least one processor to recover the first firmware. The second firmware is stored in the nonvolatile memory with higher reliability than the first firmware.

The patent application was filed on 2020-02-28 (16/804053).

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