R&D: Design Space Exploration for Balanced MLC-PCM Programming
Technique leads to 13% reduction in write latency compared to state-of-the-art method and shows good temporal consistence in different benchmarks.
This is a Press Release edited by StorageNewsletter.com on February 16, 2023 at 2:00 pmMemories – Materials, Devices, Circuits and Systems has published an article written by Jierui Ren, Beihang University, 37 Xueyuan Road, Beijing, 100191, China, Xinwei Luo, Lehigh University, 27 Memorial Drive West, Bethlehem, 18015, PA, USA, Yuanqing Cheng, Beihang University, 37 Xueyuan Road, Beijing, 100191, China, and Xiaochen Guo, Lehigh University, 27 Memorial Drive West, Bethlehem, 18015, PA, USA.
Abstract: “Multi-Level Cell Phase Change Memory (MLC PCM) is a non-volatile memory technology that promises high-density data storage. However, MLC PCM suffers from long write latency because changing the state of each memory cell takes a long time and the number of cells that can be written concurrently is limited due to the relatively large size and power consumption of the write drivers. MLC PCM typically divides the write data into multiple cell groups to program cells in batches. The group mapping has a significant impact on the overall latency of write requests. Prior work proposed a group mapping technique for single-level cell (SLC) PCM based on the data pattern of a set of applications. In this work, a larger design space of group mapping is explored for MLC PCM. The specific group mapping for each benchmark is dynamically customized. Our technique leads to a 13.14% reduction in write latency compared to the state-of-the-art method (Du et al., 2013) and shows good temporal consistence in different benchmarks.“
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