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Phison Electronics Assigned Eleven Patents

Decoding method, memory storage device, and memory control circuit unit, data writing method using different programming modes based on number of available physical erasing units, memory control circuit unit and memory storage device; data accessing method, memory control circuit unit and memory storage device, data merge method performing merge operations with identifying valid data of source nodes for next merge operation, memory storage, and control circuit unit, signal receiving circuit, memory storage and method for evaluating status of adjustment circuit for adjusting input signal, memory control, memory storage, and memory control circuit, memory storage device and management method

Decoding method, memory storage device, and memory control circuit unit
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11531589) developed by Lin, Yu-Hsiang, Yunlin County, Taiwan, for “decoding method, memory storage device, and memory control circuit unit.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: respectively performing a single-frame decoding on a plurality of first data frames read from a physical unit set, the physical unit set contains a plurality of first physical units in a rewritable non-volatile memory module, in response to an entire decoding result of the first data frames meeting a first condition, obtaining error evaluation information related to the physical unit set, and the error evaluation information reflects a bit error status of the physical unit set, obtaining reliability information according to the error evaluation information, and performing the single-frame decoding on a second data frame read from one of the first physical units according to the reliability information.

The patent application was filed on 2021-10-07 (17/495815).

Data writing method using different programming modes based on number of available physical erasing units, memory control circuit unit and memory storage device
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11467758) developed by Yang, Chieh, Taipei, Taiwan, Lin, Yi-Hsuan, Huang, Tai-Yuan, New Taipei, Taiwan, and Lin, Ping-Chuan, Taipei, Taiwan, for “data writing method using different programming modes based on the number of available physical erasing units, memory control circuit unit and memory storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.

The patent application was filed on 2019-05-29 (16/425942).

Data accessing method, memory control circuit unit and memory storage device
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11467773) developed by Li, Wei-Cheng, Shen, Yu-Chung, Miaoli County, Taiwan, and Lin, Nien-Hung, Changhua County, Taiwan, for “data accessing method, memory control circuit unit and memory storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.

The patent application was filed on 2021-02-17 (17/177214).

Data merge method performing merge operations with identifying valid data of source nodes for next merge operation, memory storage, and control circuit unit
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11455243) developed by Yeh, Chih-Kang, Kinmen County, Taiwan, for “data merge method performing data merge operations with identifying valid data of source nodes for next data merge operation, memory storage device, and memory control circuit unit.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data merge method for a rewritable non-volatile memory module including multiple physical units is provided. The method includes: starting a first data merge operation, and selecting at least one first physical unit for executing the first data merge operation and at least one second physical unit for executing a second data merge operation from the physical units, reading first mapping information from the rewritable non-volatile memory module, and copying first valid data collected from the at least one first physical unit to at least one third physical unit in the physical units, identifying second valid data in the at least one second physical unit according to the first mapping information in the first data merge operation, and starting the second data merge operation, and copying the second valid data collected from the at least one second physical unit to at least one fourth physical unit in the physical units.

The patent application was filed on 2020-12-07 (17/113122).

Data writing method, memory control circuit and memory storage
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11442662) developed by Lin, Ping-Chuan, Taipei, Taiwan, Huang, Hsiang-Jui, New Taipei, Taiwan, Hsieh, Ping-Yu, Tainan, Taiwan, and Wu, Tsung-Ju, New Taipei, Taiwan, for “data writing method, memory control circuit unit and memory storage apparatus.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a write command from a host system, and determining whether to write a data corresponding to the write command into a first area or a second area according to a write amplification factor of the first area, where if it is determined to write the data into the second area, copying the written data to the first area after writing the data.

The patent application was filed on 2020-05-22 (16/880985).

Memory control, memory storage, and memory control circuit
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11430538) developed by Lin, Yu-Hsiang, Yunlin County, Taiwan, Chou, Pochiao, Hsinchu, and Yang, Cheng-Che, New Taipei, Taiwan, for “memory control method, memory storage device, and memory control circuit unit.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data, executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data, reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data, and executing a global decoding operation on the second data according to the global parity data.

The patent application was filed on 2021-03-08 (17/195547).

Signal receiving circuit, memory storage and method for evaluating status of adjustment circuit for adjusting input signal
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11392164) developed by Chen, Sheng-Wen, Taichung, Taiwan, Sun, Shih-Yang, Taoyuan, Taiwan, and Hung, Zhen-Hong, New Taipei, Taiwan, for “signal receiving circuit, memory storage device and method for evaluating status of adjustment circuit for adjusting input signal.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.

The patent application was filed on 2020-01-08 (16/736819).

Memory control, memory storage, and memory control circuit
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11373713) developed by Zeng, Shih-Jia, Hsinchu, Taiwan, Ou, Lih Yuarn, Hsinchu County, Taiwan, Lin, Hsiao-Yi, Yilan County, Taiwan, and Lin, Wei, Taipei, Taiwan, for “memory control method, memory storage device, and memory control circuit unit.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: reading multiple first memory cells using multiple read voltage levels to obtain a first threshold voltage distribution of the first memory cells, obtaining shift information of the first threshold voltage distribution with respect to an original threshold voltage distribution of the first memory cells, obtaining first reliability information corresponding to the first threshold voltage distribution, recovering original reliability information corresponding to the original threshold voltage distribution according to a statistical characteristic of the first reliability information, adjusting the original reliability information according to the shift information to obtain second reliability information corresponding to the first threshold voltage distribution, and updating reliability information related to the first memory cells according to the second reliability information.

The patent application was filed on 2021-03-22 (17/209214).

Memory control, memory storage and memory control circuit
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11372590) developed by Lai, Chia-Hsiung, Taoyuan, Taiwan, for “memory control method, memory storage device, and memory control circuit unit.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory control method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit in response to a first read command from a host system; performing a first decoding operation on the first data to obtain decoded data corresponding to the first data; storing the decoded data corresponding to the first data in a buffer memory; reading second data from the first physical unit in response to a second read command from the host system; performing a second decoding operation on the second data; and in response to failure of the second decoding operation, searching the buffer memory for the decoded data corresponding to the first data to replace the reading of the second data.

The patent application was filed on 2020-11-26 (17/105521).

Memory control, memory storage and memory control circuit
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11347635) developed by Liang, Ming-Jen, Hsinchu, Taiwan, for “memory control method, memory storage device and memory control circuit unit.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory control method for a rewritable non-volatile memory module which includes a plurality of physical groups is provided according to an exemplary embodiment of the disclosure. The memory control method includes: storing first table information into a first physical group among the physical groups, wherein the first table information records management information corresponding to a first logical range, storing second table information into a second physical group among the physical groups, wherein the second table information also records the management information corresponding to the first logical range, and instructing a reading of the second table information from the second physical group to obtain the management information corresponding to the first logical range in response to that the first physical group is in a default status.

The patent application was filed on 2019-02-20 (16/280040).

Memory storage device and management method
Phison
Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11334290) developed by Li, Yi-Feng, Miaoli County, Taiwan, Huang, Chao-Ta, Miaoli, Taiwan, Ling, Chun-Yu, Miaoli, Taiwan, and Yeh, Jia-Huei, Miaoli County, Taiwan, for “memory storage device and management method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A management method for managing a memory storage device compatible with a PCIe (PCI Express) standard is disclosed. The memory storage device has a plurality of pins configured to couple to a host system. The management method includes: transmitting a first command to the memory storage device through at least one first pin among the pins to control the memory storage device to enter a target link status, and when the memory storage device is in the target link status, transmitting a second command to the memory storage device through a second pin among the pins to control the memory storage device to leave the target link status. The second pin is not a pin dedicated to control the memory storage device to enter or leave the target link status.

The patent application was filed on 2020-03-17 (16/820733).

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