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CEA Assigned Patent

3D memory and manufacturing process

Commissariat à l’Energie Atomique et aux Energies Alternatives (CEA), Paris, France, has been assigned a patent (11532670) developed by Barraud, Sylvain, and Andrieu, François, Grenoble, France, for “3D memory and manufacturing process.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.

The patent application was filed on 2020-12-22 (17/130006).