R&D: Exploiting Metadata to Estimate Read Reference Voltage for 3D NAND Flash Memory
Shown to reduce computational and space overhead by half; compared with using tefault read reference voltages, it is also shown to reduce RBER without exact knowledge of noise.
This is a Press Release edited by StorageNewsletter.com on December 28, 2022 at 2:00 pmIEEE Transactions on Consumer Electronics has published an article written by Yingge Li, Guojun Han, Sanwei Huang, Chang Liu, School of Information Engineering, Guangdong University of Technology, Guangzhou, China, Meng Zhang, and Fei Wu, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, China.
Abstract: “In consumer electronics, 3-D NAND flash memory has become the state-of-the-art storage medium due to the multi-bit storage per cell and 3-D stacking technology. However, flash memory cells are commonly vulnerable to numerous types of circuit-level noise, resulting in threshold voltage distribution distortion and decreased reliability. Characterization of the threshold voltage distribution and modeling of optimal read reference voltages can help to mitigate the reliability deterioration. We provide a solution for improving the reliability of flash memories while reducing their implementation cost in this paper. The proposed pre-processing method is shown to yield a smaller number of scanning voltage steps reducing the time overhead and energy consumption of multiple read operations during the characterization of threshold voltage distributions. We propose a single state asynchronous estimation (SSAE) method to estimate optimal read reference voltages. Compared with the advanced two-state asynchronous estimation (TSAE) method, it is shown to reduce the computational and space overhead by half. Furthermore, compared with using the default read reference voltages, it is also shown to reduce RBER without exact knowledge of noise.“