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STMicroelectronics Assigned Two Patents

Managing requests for access to RAM, non volatile static RAM device and corresponding control

Managing requests for access to random access memory
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11495275) developed by Eva, Christophe, Rousset, France, and Gril-Maffre, Jean-Michel, Aix-en-Provence, France, for method for managing requests for access to random access memory and corresponding system.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.

The patent application was filed on 2021-06-02 (17/336841).

Non volatile static random access memory device and corresponding control
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11488666) developed by Tailliet, François, Fuveau, France, and Battista, Marc, Allauch, France, for non volatile static random access memory device and corresponding control method.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node, and a single selection transistor coupled between the common node and a single bit line. A first output of the volatile memory cell is coupled to the common node, and a second output of the volatile memory cell, complementary to the first output, is not connected to any node outside the volatile memory cell.

The patent application was filed on 2021-01-25 (17/157631).
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