R&D: Innovative Structure to Improve Erase Speed in 3D NAND Flash Memory with Cell-on-Peri Applied

IEEE Transactions on Electron Devices has published an article written by Seonjun Choi, Department of Electronic Engineering, Hanyang University, Seoul, Republic of Korea, Changhwan Choi, Division of Materials Science and Engineering, Hanyang University, Seoul, Republic of Korea, Jae Kyeong Jeong, and Yun-Heub Song, Department of Electronic Engineering, Hanyang University, Seoul, Republic of Korea.

Abstract: “In this article, we propose silicon-nitride-pillar (SNP) and silicon-pillar (SP) structures that can be applied to a COP structure, which is the mainstay of the recent 3-D nand flash structure, by applying the IGZO-nitride-pillar (INP) and IGZO-pillar (IP) structures that showed very good erase performance announced in previous studies and verify them through device simulation. The proposed structure can supply holes through pillars formed by epitaxial growth in the P + crystal silicon subregion, which is generally used in the existing semiconductor manufacturing process. As a result of simulation, the proposed structure showed a fast erase speed of 10 μ s, and the SNP structure could prevent breakdown by appropriately controlling the thickness of the silicon nitride barrier. In addition, the SP structure with the silicon nitride barrier removed was able to maintain a fast erase speed even when the thickness of the pillar was reduced to 5 nm. Therefore, it was confirmed that the proposed structure can operate more than 100 times faster than the existing GIDL erasing structure if proper structure and operating conditions are secured.“