Micron Assigned Seventeen Patents

Memory cells for storing operational data
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,417,398) developed by Boniardi, Mattia, Cormano, Italy, Conti, Anna Maria, Milan, Italy, and Tortorelli, Innocenzo, Cernusco Sul Naviglio, Italy, for “memory cells for storing operational data.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed, and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.”

The patent application was filed on December 1, 2020 (17/108,783).

Runtime selection of memory devices and storage devices in disaggregated memory system
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,416,143) developed by Basu, Reshmi, and Murphy, Richard C., Boise, ID, for “runtime selection of memory devices and storage devices in a disaggregated memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.”

The patent application was filed on January 7, 2021 (17/143,558).

Host accelerated operations in managed NAND devices
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,409,651) developed by Jean, Sebastien Andre, Meridian, ID, and Blodgett, Greg A., Marsing, ID, for “host accelerated operations in managed NAND devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.”

The patent application was filed on May 15, 2019 (17/051,995).

Data removal marking in memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,409,462) developed by Li, Huachen, Zhang, Xu, Li, Zhong Xian, Duan, Xinghui, Wang, Xing, and Liang, Tian, Shanghai, China, for a “data removal marking in a memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).”

The patent application was filed on December 31, 2019 (16/959,064).

Forming NAND memory arrays
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,404,571) developed by Carlson, Chris M., Nampa, ID, Liu, Hung-Wei, Meridian, ID, Li, Jie, and Pavlopoulos, Dimitrios, Boise, ID, for “methods of forming NAND memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.”

The patent application was filed on October 28, 2020 (17/083,190).

Evaluation of background leakage to select write voltage in memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,404,130) developed by Gajera, Nevil N., Meridian, ID, Sarpatwari, Karthik, and Lu, Zhongyuan, Boise, ID, for an “evaluation of background leakage to select write voltage in memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold, indicating background leakage, and the second current is below a second threshold that is greater than the first threshold, indicating that the memory cell does not snap, the controller selects the second (boosted) write voltage.”

The patent application was filed on February 4, 2021 (17/167,618).

Power architecture for NVM
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,404,129) developed by Lin, Qisong, El Dorado Hills, CA, Xu, Shuai, Santa Clara, CA, Parry, Jonathan S., Binfet, Jeremy, Boise, ID, Piccardi, Michele, Cupertino, CA, and Liang, Qing, Shanghai, China, for a “power architecture for non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source, e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.”

The patent application was filed on February 5, 2021 (17/168,970).

Concurrently accessing multiple partitions of NVM
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,354,040) developed by Sundaram, Rajesh, Folsom, CA, Kau, Derchang, Cupertino, CA, Jungroth, Owen W., Sonora, CA, Chu, Daniel, Folsom, CA, Zeng, Raymond W., Sunnyvale, CA, and Qawami, Shekoufeh, El Dorado Hills, CA, for “apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.”

The patent application was filed on July 10, 2020 (16/926,431).

Copy data in memory system with AI mode
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,404,108) developed by Troia, Alberto, Munich, Germany, for “copy data in a memory system with artificial intelligence mode.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.”

The patent application was filed on May 24, 2021 (17/328,751).

Data recovery system for memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,403,169) developed by Fackenthal, Richard Edward, Carmichael, CA, and Eilert, Sean S., Penryn, CA, for a “data recovery system for memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, methods, and apparatus related to data recovery in memory devices. In one approach, a memory device encodes stored data. The memory device reads a codeword from a storage media and determines that a number errors in the codeword exceeds an error correction capability of the memory device. The errors are due, for example, to one or more stuck bits. In response to this determination, one or more data patterns are written to the storage media at the same address from which the codeword is read. The data patterns are read to identify bit locations of the stuck bits. The identified locations are used to correct bit errors of the read codeword that correspond to the identified locations. The corrected code word is sent to a host device (e.g., which requested data from the memory device using a read command).”

The patent application was filed on December 9, 2020 (17/116,969).

Self reference for ferroelectric memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,348,630) developed by Vimercati, Daniele, El Dorado Hills, CA, for a “self reference for ferroelectric memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods, systems, and apparatuses for self-referencing memory cells are described. A reference value for a cell may be created through multiple sense operations on the cell. The cell may be sensed several times and an average of at least two sensing operations may be used as a reference for another sense operation. For example, the cell may be sensed and the resulting charge stored at a capacitor. The cell may be biased to one state, sensed a second time, and the resulting charge stored at another capacitor. The cell may be biased to another state, sensed a third time, and the resulting charge stored to another capacitor. The values from the second and third sensing operations may be averaged and used as a reference value in a comparison with value of the first sensing operation to determine a logic state of the cell.”

The patent application was filed on June 15, 2021 (17/348,229).

SLC cache allocation
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,341,048) developed by Duan, Xinghui, Wang, Guanzhong, Zhang, Xu, Shanghai, China, and Yuen, Eric Kwok Fung, Dublin, CA, for a “SLC cache allocation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric, percentage of valid user data written in the device of the total user size).”

The patent application was filed on October 29, 2018 (16/488,718).

Synchronizing NAND logical-to-physical table region tracking
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,341,041) developed by Cui, Zhao, Shanghai, China, Yuen, Eric Kwok Fung, Dublin, CA, Wang, Guan Zhong, Duan, Xinghui, Shanghai, China, D’Eliseo, Giuseppe, Caserta, Italy, and Ferrari, Giuseppe, Naples, Italy, for “synchronizing NAND logical-to-physical table region tracking.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.”

The patent application was filed on July 27, 2020 (16/940,015).

Memories having multiple voltage generation systems connected to voltage regulator
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,335,415) developed by Piccardi, Michele, Cupertino, CA, for “memories having multiple voltage generation systems connected to a voltage regulator.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Memories having an array of memory cells might include a plurality of voltage generation systems each having a respective output selectively connected to a respective access line, and a voltage regulator having an input connected to the output of each of the voltage generation systems, and having an output selectively connected to the respective access line for each of the voltage generation systems.”

The patent application was filed on November 24, 2020 (17/102,602).

Memory tiering using PCIe connected far memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,379,373) developed by Ray, Anirban, Santa Clara, CA, Stonelake, Paul, San Jose, CA, Mittal, Samir, Palo Alto, CA, and Anand, Gurpreet, Pleasanton, CA, for a “memory tiering using PCIe connected far memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.”

The patent application was filed on August 13, 2019 (16/539,139).

Selective relocation of data of subset of data block based on distribution of reliability statistics
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,379,122) developed by Malshe, Ashutosh, Muchherla, Kishore Kumar, Fremont, CA, Rayaprolu, Vamsi Pavan, San Jose, CA, and Singidi, Harish R., Fremont, CA, for a “selective relocation of data of a subset of a data block based on distribution of reliability statistics.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A set of memory cells in a data block of a memory component is sampled. A distribution statistic is generated for the data block based on a reliability statistic for each of the set of sampled memory cells. A determination is made based on the distribution statistic of whether the read disturb stress is uniformly or non-uniformly distributed across the data block. In response to a determination that the read disturb stress is non-uniformly distributed across the data block, a first subset of the data block is relocated to another data block of the memory component. The first subset of the data block is associated with a higher concentration of read disturb stress than other subsets of the data block.”

The patent application was filed on February 18, 2021 (17/178,976).

Enhanced duplicate write data tracking for cache memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,314,643) developed by Walker, Robert M., Raleigh, NC, for an “enhanced duplicate write data tracking for cache memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A request to perform a write operation to write data at a memory sub-system is received. Responsive to the request to perform the write operation, the data is stored at a cache portion of cache memory of the memory sub-system. A duplicate copy of the data is stored at a write buffer portion of cache memory. An entry of the write buffer record is recorded that maps a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory. A memory operation is performed at the memory sub-system based at least in part on the write buffer record.”

The patent application was filed on July 21, 2020 (16/934,837).