Kepler Computing Assigned Patent

Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11,423,967) developed by Dokania, Rajeev Kumar, Beaverton, OR, Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Pandey, Pratyush, Kensington, CA, Olaosebikan, Debo, San Francisco, CA, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for “stacked ferroelectric non-planar capacitors in a memory bit-cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where `n` is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.”

The patent application was filed on June 25, 2021 (17/359,311).