IEEE Transactions on Electron Devices has published an article written by Kihoon Nam, Chanyang Park, Jun-Sik Yoon, Giho Yang; Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, South Korea, Min Sang Park, SK hynix Inc., Icheon 17336, South Korea, and Rock-Hyun Baek, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, South Korea.
Abstract: “In this study, to improve the threshold voltage ( Vth ) variability and cell performance in three-dimensional (3-D) NAND flash memory, we analyzed the electrical characteristics with respect to various channel thickness ( Tch ) and average grain size (GS) values. The 3-D random Voronoi grain patterns were applied to a polycrystalline silicon (poly-Si) channel to determine the actual grain shape using technology computer-aided design (TCAD). For statistical analysis, key electrical characteristics such as the threshold voltage ( Vth ), subthreshold swing (SS), maximum transconductance ( gm ), and on-current ( ION ) were extracted from samples with different patterns of grain boundaries (GBs) at specific Tch and GS values. The standard deviation of Vth ( σVth ) increased with an increase in GS at Tch>22 nm, and no increase trend was observed for σVth at Tch<22 nm. The mean SS, gm , and ION related to the performance improved overall with an increase in GS at the same Tch value. Based on a comprehensive analysis of various 3-D grain patterns, optimal structures were proposed in terms of variability and/or performance. Furthermore, based on the results, we suggest suitable Tch and GS parameters for the given target of 3-D NAND flash devices.“