Panasonic Assigned Two Patents

NVM device and challenge response method
Panasonic Holdings Corp., Osaka, Japan, has been assigned a patent (11,404,119) developed by Yoshimoto, Yuhei, Hyogo, Japan, and Katoh, Yoshikazu, Osaka, Japan, for “non-volatile memory device and challenge response method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device includes a data generation circuit and a reconfiguration processing circuit. The data generation circuit generates: third response data that is different from the first response data, PUF registration mode, when the reconfiguration writing is executed by the reconfiguration processing circuit and the first type of challenge data is obtained again after the reconfiguration writing is executed, after the first response data is generated, and fourth response data that is identical to the second response data, permanent PUF registration mode, when the reconfiguration writing is executed by the reconfiguration processing circuit and the second type of challenge data is obtained again after the reconfiguration writing is executed, after the second response data is generated.”

The patent application was filed on April 23, 2021 (17/239,026).

Variable resistance NVM
Panasonic Corp., Osaka, Japan, has been assigned a patent (11,062,772) developed by Mochida, Reiji, Kouno, Kazuyuki, Ono, Takashi, Osaka, Japan, Nakayama, Masayoshi, Kyoto, Japan, and Hayata, Yuriko, Osaka, Japan, for a “variable resistance non-volatile memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.”

The patent application was filed on December 5, 2018 (16/957,830).