R&D: TLC Charge Trap Flash Memory Device with CVD-Grown MoS2

Results in Physics has published an article written by Minkyung Kim, Eunpyo Park, Jongkil Park, Jaewook Kim, YeonJoo Jeong, Suyoun Lee, Inho Kim, Jong-Keuk Park, Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea, Sung-YunPark, College of Engineering, Electronics Engineering, Pusan National University, Busan 46241, South Korea, Joon Young Kwak, Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea, and Division of Nanoscience and Technology, Korea University of Science and Technology (UST), Daejeon 34113, South Korea.

Abstract: “This study investigates the triple-level cell (TLC) memory retention of a MoS₂-channel based charge trap flash (CTF) device. A top-gated CTF device with a high-κ gate dielectric is found to have a high coupling ratio, which enhances the tunneling efficiency for programming. The fabricated devices show the long memory retention performance for each state, demonstrating the feasibility of a robust TLC CTF memory device based on a CVD grown 2D material.“