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R&D: Toward 7 Bits/Cell, Synergistic Improvement of 3D Flash Memory by Combination of Single-Crystal Channel and Cryogenic Operation

Ultra-multi-level cell of 7 bits per cell is demonstrated for first time, and its feasibleness in future storage products is shown.

IEEE Xplore has published, in 2022 IEEE International Memory Workshop (IMW) proceedings, an article written by Hitomi Tanaka, Yuta Aiba, Takashi Maeda, Kensuke Ota, Yusuke Higashi, Institute of Memory Technology Research and Development, Kioxia Corporation, Japan, Keiichi Sawa, Fumie Kikushima, Masayuki Miura, Memory Div., Kioxia Corporation, Japan, and Tomoya Sanuki, Institute of Memory Technology Research & Development, Kioxia Corporation, Japan.

Abstract: In this paper, it is shown that the combination of single-crystal channel and cryogenic operation at 77 K using liquid nitrogen improves the cell transistor characteristics and the storage performance of 3D Flash memory. Compared to the cryogenic operation with poly-Si channels, that we have already reported, the cryogenic operation with single-crystal channels results in a steepening of the cell transistor subthreshold slope and reduced read noise. In particular, read noise is significantly suppressed to one-third due to the synergistic effect of the improvement by single-crystal and the cryogenic operation, compared with poly-Si channel in room temperature. Furthermore, data retention is improved at cryogenic temperature compared to room temperature. These improvements lead to a narrower Vth distribution of the cell, which enables bit-cost scaling through a multi-level cell. An ultra-multi-level cell of 7 bits per cell is successfully demonstrated for the first time, and its feasibleness in future storage products is shown.

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