R&D: Novel Program Scheme to Optimize Program Disturbance in Dual-Deck 3D NAND Flash Memory

IEEE Electron Device Letters has published an article written by Xinlei Jia, Lei Jin, Jianquan Jia, Kaikai You, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China, and School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China, and Yangtze Memory Technologies Company Ltd., Wuhan 430205, China, Kaiwei Li, Shan Li, Yali Song, Yuanyuan Min,Ying Cui, Wenzhe Wei, Xiangnan Zhao, Weiming Chen, Hongtao Liu, An Zhang, Yangtze Memory Technologies Company Ltd., Wuhan 430205, China, and Zongliang Huo, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China, and School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China, and Yangtze Memory Technologies Company Ltd., Wuhan 430205, China.

Abstract: “The dual-deck architecture with aligned upper and lower decks is considered a promising technology to meet the demand of increasing word-line (WL) layers of 3D NAND flash. However, the relevant reliability studies are still lacking for the dual-deck 3D NAND array. In this work, it is reported an abnormal program disturbance phenomena of the bottom WLs in the upper-deck, and the physical mechanisms were studied. According to experimental analysis and TCAD simulations, the un-programmed dummy WLs at the joint region can introduce excessive joint residual electrons in the channel before the program, resulting in insufficient channel self-boosting potential, which is responsible for the degraded program disturbance. Thus, a novel program scheme is proposed to alleviate the program disturbance, which has been validated by experiments.“