Fadu Assigned Two Patents

Memory controller and storage device
Fadu Inc., Seoul, Korea, has been assigned a patent (11,348,658) developed by Kim, Hongseok, Seoul, Korea, Park, Sang Hyun, Hwaseong-si, Korea, Hong, Sunggil, Lim, Hayoung, and Nam, EHyun, Seoul, Korea, for “memory controller and storage device including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory controller and a storage device including the same are provided. The memory controller performs decoding by selecting a decoder of a level enough to correct bit errors in a codeword from among a plurality of error correction code, ECC) decoders based on a bit error history of a non-volatile memory device.”

The patent application was filed on June 28, 2021 (17/359,924).

Memory system including flash memory and controller
Fadu Inc., Seoul, Korea, has been assigned a patent (11,322,220) developed by Kim, Hongseok, Rha, Kyoungseok, and Nam, EHyun, Seoul, Korea, for “memory system including a flash memory device and a memory controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system is provided. In the memory system, a memory controller transmits a write enable signal and a data strobe signal to a flash memory device, a command or an address is transmitted at a rising edge or a falling edge of the write enable signal through a data line in a single data rate (SDR) scheme, and input data is transmitted at each of a rising edge and a falling edge of the data strobe signal through the data line in a double data rate (DDR) scheme. The memory controller includes a parity signal generation unit configured to receive the write enable signal transmitted in the DDR scheme and output a parity signal by generating a first parity bit for the input data. The flash memory device includes a bit error detection unit configured to receive the parity signal output from the memory controller, generate a second parity bit for the input data received by the flash memory device, and determine whether a bit error has occurred to the input data by performing a parity check.”

The patent application was filed on November 20, 2020 (16/953,485).