R&D: FELIX: Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration

ACM Transactions on Embedded Computing Systems has published an article written by Taha Soliman, Robert Bosch GmbH, Germany, Nellie Laleni, Fraunhofer IPMS, Center Nanoelectronic Technologies, Germany, Tobias Kirchner, Robert Bosch GmbH, Germany, Franz Müller, Ashish Shrivastava, Thomas Kämpfe, Fraunhofer IPMS, Center Nanoelectronic Technologies, Germany, Andre Guntoro, Robert Bosch GmbH, Germany, and Norbert Wehn, University of Kaiserslautern, Germany.

Abstract: “Today, a large number of applications depend on deep neural networks (DNN) to process data and perform complicated tasks at restricted power and latency specifications. Therefore, processing-in-memory (PIM) platforms are actively explored as a promising approach to improve the throughput and the energy efficiency of DNN computing systems. Several PIM architectures adopt resistive non-volatile memories as their main unit to build crossbar-based accelerators for DNN inference. However, these structures suffer from several drawbacks such as reliability, low accuracy, large ADCs/DACs power consumption and area, high write energy, etc. In this paper, we present a new mixed-signal in-memory architecture based on the bit-decomposition of the multiply and accumulate operations. Our in-memory inference architecture uses a single FeFET as a non-volatile memory cell. Compared to the prior work, this system architecture provides a high level of parallelism while using only 3-bit ADCs. Also, it eliminates the need for any DAC. In addition, we provide flexibility and a very high utilization efficiency even for varying tasks and loads. Simulations demonstrate that we outperform state-of-the-art efficiencies with 36.5 TOPS/W and can pack 2.05 TOPS with 8-bit activation and 4-bit weight precision in an area of 4.9 mm² using 22 nm FDSOI technology. Employing binary operation, we obtain 1169 TOPS/W and over 261 TOPS/W/mm² on system level..“