China Flash Assigned Two Patents

Programming NAND flash memory
China Flash Co., Ltd., Shanghai, China, has been assigned a patent (11,355,196) developed by Nie, Hong, and Chen, Jingwei, Shanghai, China, for a “method for programming NAND flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to a method for programming a NAND flash memory, which includes: providing a NAND flash memory array, and initializing a to-be-programmed memory cell; applying a drain voltage to the drain of the to-be-programmed memory cell, and floating the source of the to-be-programmed memory cell; and applying a programming voltage to the gate of the to-be-programmed memory cell, and discharging the voltage at each end of the to-be-programmed memory cell after maintaining the voltage for a first time period, to complete programming; a difference between the voltage applied to the drain and the voltage applied to the substrate of the to-be-programmed memory cell being not less than 4 V, the first time period being not longer than 100 .mu.s, and the programming voltage being not higher than 10 V.”

The patent application was filed on July 20, 2021 (17/380,720).

Programming B4 flash memory
China Flash Co., Ltd., Shanghai, China, has been assigned a patent (11,348,645) developed by Nie, Hong, and Chen, Jingwei, Shanghai, China, for a “method for programming B4 flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for programming a B4 flash memory includes: floating a source of a P-channel flash memory device, separately applying voltages to a gate, a drain, and a bulk of the P-channel flash memory device, and injecting holes into the bulk, so that electrons are gathered in the drain to form primary electrons, separately applying voltages to the drain and the bulk, so that an electric field is formed between the drain and the bulk, where the holes accelerate downward under the action of the electric field and impact the bulk in the P-channel flash memory device to generate secondary electrons, and separately applying voltages to the gate and the bulk of the P-channel flash memory device, so that the secondary electrons form tertiary electrons under the action of the electric field in a vertical direction, where the tertiary electrons are superposed with the primary electrons to be injected into a floating gate.”

The patent application was filed on September 2, 2021 (17/465,272).