IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems has published an article written by Sivert T. Sliper, School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ U.K., William Wang, Nikos Nikoleris, Arm Research, Cambridge, CB1 9NJ, U.K., Alex S. Weddell, School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ U.K., Anand Savanth, Pranay Prabhat, Arm Research, Cambridge, CB1 9NJ, U.K., and Geoff V. Merrett, School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ U.K.
Abstract: “Intermittent computing (IC) is a key enabler for the vision of a trillion Internet of Things devices. By harvesting energy from the environment, and leveraging non-volatile memory (NVM) to retain computational progress across power cycles, IC enables untethered and battery-free devices to perform computation whenever ambient energy is available. The backbone of state retention is NVM, and recent advances in energy-efficient NVM have the potential to expand the application domain of IC significantly. Utilizing emerging NVM at the level of bitcells, researchers have proposed non-volatile processors. However, these do not leverage hardware-software co-design, which can be used to overcome hardware limitations and to provide support for application-level constraints such as atomicity. In this paper, we propose MEMIC, a memory architecture tailored for IC devices with byte-addressable NVM. A core focus of MEMIC is to combine volatile-and non-volatile memory in such a way that the operations of IC are as efficient as possible, while also maximizing computational performance per joule. MEMIC uses volatile memory for energy efficiency, and nonvolatile memory for data retention. To avoid double-buffered checkpoints and costly roll-backs when code needs to be reexecuted, MEMIC is designed to track and minimize writes to non-volatile memory during failure-atomic sections. Our evaluation shows that MEMIC’s instruction cache reduces workload completion time under intermittent operation by 41-70% and its data cache provides a further reduction of 13-39%.“