Ceremorphic Assigned Patent
Flash and RAM allocation for reduced power consumption in processor
By Francis Pelletier | June 9, 2022 at 2:00 pmCeremorphic, Inc., San Jose, CA, has been assigned a patent (11,307,779) developed by Kallam, Subba Reddy, Murali, Partha Sarathy, Sunnyvale, CA, Pulagam, Venkata Siva Prasad, Secunderabad, India, Biyyani, Anusha, Hyderabad, India, Vinjamuri, Venkatesh, Tenil, India, Mohammed, Shahabuddin, Hyderabad, India, Gurram, Rahul Kumar, Secunderabad, India, and Soni, Akhil, Kalpi, India, for “system and method for flash and RAM allocation for reduced power consumption in a processor.“
The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.”
The patent application was filed on August 13, 2020 (16/992,098).
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