STMicroelectronics Assigned Four Patents

Memory cell comprising phase-change material
STMicroelectronics, Crolles (2) SAS, Crolles, France, has been assigned a patent (11,329,225) developed by Hinsinger, Olivier, Barraux, France, for a “memory cell comprising a phase-change material.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.”

The patent application was filed on September 4, 2020 (17/012,558)

Bit-line voltage generation circuit for NVM
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11,322,201) developed by Perroni, Maurizio Francesco, Messina, Italy, Disegni, Fabio Enrico Carlo, Spino d’adda, Italy, La Placa, Michele, Cefalu’, Italy, and Torti, Cesare, Pavia, Italy, for “bit-line voltage generation circuit for a non-volatile memory device and corresponding method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline, associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal, a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.”

The patent application was filed on January 27, 2021 (17/159,381).

NVM including row decoder with pull-up stage controlled by current mirror
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11,289,158) developed by Disegni, Fabio Enrico Carlo, Spino d’adda, Italy, Perroni, Maurizio Francesco, Messina, Italy, Torti, Cesare, Pavia, Italy, and Manfre, Davide, Pandino, Italy, for a “non-volatile memory device including a row decoder with a pull-up stage controlled by a current mirror.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal, and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node, and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.”

The patent application was filed on December 16, 2020 (17/123,518).

NVM having reading circuit operating at low voltage
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11,282,573) developed by Manfre’, Davide, Pandino, Italy, Capecchi, Laura, Vedano al Lambro, Italy, Carissimi, Marcella, Treviolo, Italy, and Pasotti, Marco, Travaco’ Siccomario, Italy, for a “non-volatile memory device having a reading circuit operating at low voltage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device includes a memory array, a reading circuit, a column decoder stage, and a read supply voltage generator. The column decoder stage includes selectable bitlines and selection switches. A read supply voltage generator includes a voltage regulation circuit and a dummy column decoder coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path. The voltage regulation circuit is configured to receive a first electrical quantity correlated to a desired voltage value on the selected bitline and a second electrical quantity correlated to a desired current value for the selected bitline and to generate a regulated read supply voltage for the column decoder stage.”

The patent application was filed on June 18, 2020 (16/904,869).