R&D: Retention Failure Recovery Technique for 3D TLC NAND Flash Via Wordline Interference

Solid-State Electronics has published an article written by Liu Yang, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China, and University of Chinese Academy of Science, Beijing, China, Qi Wang, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China, University of Chinese Academy of Science, Beijing, China, and Yangtze Memory Technologies Co. Ltd, Beijing, China, Qianhui Li, Jing He, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China, and University of Chinese Academy of Science, Beijing, China, and Zongliang Huo, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China, University of Chinese Academy of Science, Beijing, China, and Yangtze Memory Technologies Co. Ltd, Beijing, China. 

Abstract: “The non-volatility of NAND flash memory is guaranteed only when data errors are within the ECC correction capability. With data errors exceeding ECC correction capability due to the retention process, the data recovery technique is a straightforward way to reduce retention errors to be correctable by ECC. In this paper, a high-efficient data recovery technique is proposed. Firstly, the WL Interference (WI) is utilized to recharge retention-failed cells. Retention errors are reduced with low operation latency. Secondly, the rewriting part in the data recovery technique is optimized by adaptively increasing the program verify voltage. Retention time is thus extended. The experimental results show that the proposed data recovery technique outperforms the state-of-the-art ADROP technique in both data recovery efficiency and capability by 12.92x and 2.28x respectively. In the 3K PE cycles condition, the retention time is extended by 83.3x at most with proposed technique, which is 2.6x longer than the ADROP technique.“