R&D: Optimal Read Voltages Decision Scheme Eliminating Read Retry Operations for 3D NAND Flash Memories

Microelectronics Reliability has published an article written by Qianhu iLi , Qi Yang, Xiaolei Yu, Yiyang Jiang, Jing, He, and Zongliang Huo, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China, and University of Chinese Academy of Sciences, Beijing 100049, China.

Abstract: “Read error increment due to threshold voltage degradation is one of the primary reliability issues of 3D NAND flash memories. Read retry technique which reduces read errors by determining the optimal read voltages (ORVs) is an effective means to solve the problem. However, the extra read operations required by read retry increase the read latency in data read and recovery process. Here, we proposed an ORVs decision scheme without specific read retry operations (ORVD-WRRO) to eliminate the read operations required by read retry and thus decrease the read latency. ORVD-WRRO uses the proposed overlap-error-record error-correcting-code (OER-ECC) to determine the ORVs. Besides, ORVD-WRRO adds ORVs decision and modification operations between read sensing operations and the previous read and decoded data by OER-ECC can be used to determine the subsequent ORVs. Thus, the ORVs of the NAND flash memory can be determined without any extra read operations addition. Experimental results show that the deviations between ORVs determined by the proposed ORVD-WRRO and the true value of the ORVs is smaller than 44mV and the raw bit error rate (RBER) is reduced to less than 0.0087 which is within the error correction capability of QC-LDPC(8255, 8890). Moreover, the proposed scheme can reduce the read and data recovery latency by 23.21% compared with the conventional scheme.“