Tokyo Electron Assigned Patent

Tokyo Electron Limited, Tokyo, Japan, has been assigned a patent (11,282,828) developed by Gardner, Mark I., Cedar Creek, TX, and Fulford, H. Jim, Marianna, FL, for “high density architecture design for 3D logic and 3D memory circuits.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with 3D NAND devises are fabricated on a first wafer, and high voltage and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.”

The patent application was filed on August 19, 2020 (16/997,525).