R&D: Novel Program Suspend Scheme for Improving Reliability of 3D NAND

IEEE Journal of the Electron Devices Society has published an article written by Zhichao Du, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing, China, University of Chinese Academy of Sciences, Beijing, China, and Yangtze Memory Technologies Company, Ltd., Wuhan, China, Zhipeng Dong, Yangtze Memory Technologies Company, Ltd., Wuhan, China, Kaikai You, Xinlei Jia, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing, China, University of Chinese Academy of Sciences, Beijing, China, and Yangtze Memory Technologies Company, Ltd., Wuhan, China, Ye Tian, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing, China, University of Chinese Academy of Sciences, Beijing, China, and Yangtze Memory Technologies Company, Ltd., Wuhan, China, Yu Wang, Zhaochun Yang, Xiang Fu, Yangtze Memory Technologies Company, Ltd., Wuhan, China, Fei Liu, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing, China, Qi Wang, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing, China, University of Chinese Academy of Sciences, Beijing, China, and Yangtze Memory Technologies Company, Ltd., Wuhan, China, Lei Jin, and Zongliang Huo, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing, China, University of Chinese Academy of Sciences, Beijing, China, and Yangtze Memory Technologies Company, Ltd., Wuhan, China.

Abstract: “Experimental results indicate that the conventional program suspend scheme in 3D NAND flash memory chip can generate unexpected additional read fail bits and reduce the reliability of 3D NAND flash memory. These extra read fail bits are observed when the program suspend command is issued during the program stage, and particularly, they become more obvious as the delay time between program suspend operation and other following operations exceeds tens of milliseconds. By analyzing the waveform of conventional program suspend scheme, it is suggested that the unexpected extra read fail bits are caused by the different occupancy of grain boundary traps (GBTs) in the polycrystalline silicon (poly-Si) channel during the idle time after the program suspend operation. Accordingly, a novel program suspend scheme is proposed by adding a ‘stabilizing’ pulse immediately after the program stage. Silicon experimental data show that the proposed scheme can effectively limit the read fail bit count (FBC) to a normal range, thus improving the reliability of 3D NAND flash memory significantly.“