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Texas Instruments Assigned Two Patents

Customizable backup and restore from nonvolatile logic array, nonvolatile logic memory for computing module reconfiguration

Customizable backup and restore from nonvolatile logic array
Texas Instruments, Inc., Dallas, TX, has been assigned a patent (11,244,710) developed by Bartling, Steven Craig, Plano, TX, and Khanna, Sudhanshu, Richardson, TX, for customizable backup and restore from nonvolatile logic array.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

The patent application was filed on April 4, 2016 (15/089,607).

Nonvolatile logic memory for computing module reconfiguration
Texas Instruments, Inc., Dallas, TX, has been assigned a patent (11,243,903) developed by Waechter, Andreas, Jung, Mark, Bavaria, Germany, Bartling, Steven Craig, and Khanna, Sudhanshu, Plano, TX, for a nonvolatile logic memory for computing module reconfiguration.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Configuration states for a computing device and/or associated peripherals (profiles) are stored in one or more non-volatile logic (NVL) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

The patent application was filed on October 21, 2019 (16/658,928).

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