NEO Semiconductor Assigned Patent
Reading NAND flash memoryBy Francis Pelletier | March 25, 2022 at 2:00 pm
NEO Semiconductor, Inc., San Jose, CA, has been assigned a patent (11,232,835) developed by Hsu, Fu-Chang, San Jose, CA, for “methods and apparatus for reading NAND flash memory.“
The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatus for reading NAND flash memory are disclosed. In an embodiment, a method is provided for reading a NAND flash memory that includes strings of memory cells that are coupled to bit lines and word lines. The method includes precharging a plurality of bit lines to a precharge voltage level, and applying a sequence of word line voltages to a selected word line. The method also includes initiating discharge of one or more bit lines associated with one or more cells, respectively. The method also includes controlling discharging current of discharging bit lines to achieve identical discharge rates, waiting for a discharging time period for each bit line that is discharging, and latching bit line data at an end of each discharge time period.”
The patent application was filed on July 14, 2020 (16/928,996).