Radian Memory Assigned Five Patents

Zone-specific configuration of maintenance by nonvolatile memory controller
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11,237,978) developed by Lercari, Robert, Thousand Oaks, CA, Chen, Alan, Simi Valley, CA, Jadon, Mike, Manhattan Beach, CA, Robertson, Craig, Simi Valley, CA, and Kuzmin, Andrey V., Moscow, Russia, for a “zone-specific configuration of maintenance by nonvolatile memory controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on March 27, 2020 (16/833,416).

Configuration of NVM as virtual devices with user defined parameters
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11,221,961) developed by Lercari, Robert, Thousand Oaks, CA, Chen, Alan, Simi Valley, CA, Jadon, Mike, Manhattan Beach, CA, Robertson, Craig, Simi Valley, CA, and Kuzmin, Andrey V., Moscow, Russia, for a “configuration of nonvolatile memory as virtual devices with user defined parameters.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on March 27, 2020 (16/833,408).

NVM controller enabling independent garbage collectionto independent zones or isolated regions
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11,221,960) developed by Lercari, Robert, Thousand Oaks, CA, Chen, Alan, Simi Valley, CA, Jadon, Mike, Manhattan Beach, CA, Robertson, Craig, Simi Valley, CA, and Kuzmin, Andrey V., Moscow, Russia, for a “nonvolatile memory controller enabling independent garbage collection to independent zones or isolated regions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on March 3, 2020 (16/808,317).

NVM controller supporting variable configurability and forward compatibility
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11,221,959) developed by Lercari, Robert, Thousand Oaks, CA, Chen, Alan, Simi Valley, CA, Jadon, Mike, Manhattan Beach, CA, Robertson, Craig, Simi Valley, CA, and Kuzmin, Andrey V., Moscow, Russia, for a “nonvolatile memory controller supporting variable configurability and forward compatibility.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on March 3, 2020 (16/808,304).

Maintenance of non-volatile memory on selective namespaces
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11,216,365) developed by Kuzmin, Andrey V., Moscow, Russia, and Wayda, James G., Laguna Niguel, CA, for a “maintenance of non-volatile memory on selective namespaces.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to ‘plan ahead’ in a manner supporting host issuance of true multi-plane read commands.”

The patent application was filed on March 28, 2020 (16/833,547).