STMicroelectronics Assigned Ten Patents

Writing electrically erasable and programmable non volatile memory and corresponding integrated circuit
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,238,944) developed by Tailliet, Francois, Fuveau, France, and Ameziane El Hassani, Chama, Aix en Provence, France, for “method for writing an electrically erasable and programmable non volatile memory and corresponding integrated circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.”

The patent application was filed on March 19, 2020 (16/824,268).

Memory cell
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11,227,992) developed by Cappelletti, Paolo Giuseppe, Seveso, Italy, for a “memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A phase-change memory cell is formed by a heater, a crystalline layer disposed above the heater, and an insulating region surrounding sidewalls of the crystalline layer. The phase-change memory cell supports programming with a least three distinct data levels based on a selective amorphization of the crystalline layer.”

The patent application was filed on Filed: May 26, 2020 (16/883,190).

Storage device
STMicroelectronics (Grenoble 2) SAS, Grenoble, France, has been assigned a patent (11,211,932) developed by El Haddad, Elias, Tromelin, Tanguy, Grenoble, France, Bougant, Patrick, Saint Egreve, France, and Matheron, Christophe, Voreppe, France , for a “storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A device includes an AND logic gate and a D latch. The AND logic gate includes a first input configured to be coupled to a third-party device to receive a selection signal, a second input configured to be coupled to the third-party device to receive a status signal, and an output configured to transmit an output signal when the selection signal and the status signal are received. The D latch is capable of storing datum. The D latch includes an activation input coupled to the output of the AND logic gate and a data input configured to be coupled to the third-party device to receive a data signal that is representative of the datum. The D latch is configured to store the datum in response to the output signal.”

The patent application was filed on Filed: November 18, 2020 (16/951,645).

Managing memory space of memory device and corresponding system
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,189,360) developed by Gril-Maffre, Jean-Michel, Aix-en-Provence, france, and Eva, Christophe, Rousset, France, for “method for managing the memory space of a memory device and corresponding system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.”

The patent application was filed on Filed: October 30, 2019 (16/669,184).

Erasing non-volatile memory
STMicroelectronics S.R.L., Agrate Brianza, Italy, has been assigned a patent (11,183,255) developed by Matranga, Giovanni, Catania, Italy, Lo Giudice, Gianbattista, Pedara, Italy, Grasso, Rosario Roberto, S. Agata Li Battiati, Italy, and Di Martino, Alberto Jose’, Palagonia, Italy, for “methods and devices for erasing non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value, and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.”

The patent application was filed on Filed: July 9, 2020 (16/925,059).

Electronic chip memory
STMicroelectronics SA, Montrouge, France, has been assigned a patent (11,164,647) developed by Denorme, Stephane, Crolles, France, and Candelier, Philippe, St Mury Monteymond, France, for an “electronic chip memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A device includes a number of irreversibly programmable memory points. Each irreversibly programmable memory point includes a first semiconductor zone and a gate located on the first zone. A conductive area defines the gates of the memory points. First and second semiconductor areas are respectively located on either side of a vertical alignment with the conductive area. The first zones are alternately in contact with the first and second areas.”

The patent application was filed on filed: December 13, 2019 (16/713,947).

Addressing non-volatile memory on I.sup.2C bus and corresponding
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,127,468) developed by Tailliet, Francois, Fuveau, France, and Battista, Marc, Allauch, France, for a “method for addressing a non-volatile memory on I.sup.2C bus and corresponding.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I.sup.2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.”

The patent application was filed on filed: December 14, 2017 (15/842,586).

Writing in volatile memory and corresponding integrated circuit
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,120,887) developed by Eva, Christophe, Rousset, France, and Gril-Maffre, Jean-Michel, Aix-en-Provence, France, for “method for writing in a volatile memory and corresponding integrated circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code, storing in a buffer register the data to be written to the memory, and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.”

The patent application was filed on filed: November 12, 2020 (17/096,090).

Process for fabricating resistive memory cells
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,114,614) developed by Boivin, Philippe, Venelles, France, for a “process for fabricating resistive memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.”

The patent application was filed on Filed: May 1, 2019 (16/400,649).

Resistive memory cell having ovonic threshold switch
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,114,502) developed by Boivin, Philippe, Venelles, France, for a “resistive memory cell having an ovonic threshold switch.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.”

The patent application was filed on Filed: September 10, 2019 (16/566,794).